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W3H64M72E-400ES Datasheet(PDF) 5 Page - White Electronic Designs Corporation

Part # W3H64M72E-400ES
Description  64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

W3H64M72E-400ES Datasheet(HTML) 5 Page - White Electronic Designs Corporation

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W3H64M72E-XSBX
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
TABLE – 1 BALL DESCRIPTIONS (continued)
A0-A12
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA2–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD
MODE command.
DQ0-71
I/O
Data input/output: Bidirectional data bus
UDQS, UDQS#
I/O
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
LDQS, LDQS#
I/O
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
VCC
Supply
Power Supply: 1.8V ±0.1V
VCCQ
Supply
DQ Power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity
VREF
Supply
SSTL_18 reference voltage.
VSS
Supply
Ground
NC
-
No connect: These balls should be left unconnected.
DNU
-
Future use; address bits A14 and A15 are reserved for future densities.


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