9

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WC32P020-XXM

December 2002

Rev. 2

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

NOTES:

1. This number can be reduced to 5ns if strobes have equal loads.

2. If the asynchronous setup time (#47A) requirements are satisfied, the DSACKx#

low data setup time (#31) and DSACKx# low to BERR# low setup time (#48) can be

ignored. The data must only satisfy the data-in to clock low setup time (#27) for the

following clock cycle, and BERR# must only satisfy the late BERR low to clock low

setup time (#27A) for the following clock cycle.

3. This parameter specifies the maximum allowable skew between DSACK0# to

DSACK1# asserted or DSACK1# to DSACK0# asserted; specification #47A must be

met by DSACK0# or DSACK1#.

4. This specification applies to the first (DSACK0# or DSACK1#) DSACKx# signal

asserted. In the absence of DSACKx#, BERR# is an asynchronous input setup time

(347A).

5. DBEN# may stay asserted on consecutive write cycles.

6. The minimum values must be met to guarantee proper operation. If this maximum

value is exceeded, BG may be reasserted.

7. This specification indicates the minimum high time for ECS# and OCS# in the event

of an internal cache hit followed immediately by a cache miss or operand cycle.

8. This specification guarantees operation with the 68881/68882, which specifies a

minimum time for DS# negated to AS# asserted. Without this specification, incorrect

interpretation of specifications #9A and #15 would indicate that the WC32P020-XXM

does not meet the 68881/68882 requirements.

9. This specification allows a system designer to guarantee data hold times on the

output side of data buffers that have output enable signals generated with DBEN#.

10. These specifications allow system designers to guarantee that an alternate bus

master has stopped driving the bus when the 68020 regains control of the bus after

an arbitration sequence.

11. This specification allows system designers to qualify the CS# signal of an

68881/68882 with AS# (allowing 7 ns for a gate delay) and still meet the CS# to

DS# setup time requirement.

AC ELECTRICAL SPECIFICATIONS – READ AND WRITE CYCLES (CONT'D)

Characteristic

Specification

16.67 MHz

20 MHz

25MHz

Unit

Min

Max

Min

Max

Min

Max

BGACK# Asserted to BR# Negated

37A (6)

0

1.5

0

1.5

0

1.5

Clks

BG Width Negated

39

90

–

75

–

60

–

ns

BG# Width Asserted

39A

90

–

75

–

60

–

ns

Clock High to DBEN# Asserted (Read)

40

0

30

0

25

0

20

ns

Clock High to DBEN# Negated (Read)

41

0

30

0

25

0

20

ns

Clock High to DBEN# Asserted (Write)

42

0

30

0

25

0

20

ns

Clock High to DBEN# Negated (Write)

43

0

30

0

25

0

20

ns

R/W# Low to DBEN# Asserted (Write)

44

15

–

10

–

10

–

ns

DBEN# Width Asserted

Read

45 (5)

60

–

50

–

40

–

ns

Write

120

–

100

–

80

–

R/W# Width Valid (Write or Read)

46

150

–

125

–

100

–

ns

Asynchronous Input Setup Time

47A

5–5–5–

ns

Asynchronous Input Hold Time

47B

15

–

15

–

10

–

ns

DSACKx# Asserted to BERR#, HALT# Asserted

48 (4)

–

30

–

20

–

18

ns

Data Out Hold from Clock High

53

0–0–0–

ns

R/W# Valid to Data Bus Impedance Change

55

30

–

25

–

20

–

ns

RESET# Pulse Width (Reset Instruction)

56

512

–

512

–

512

–

Clks

BERR# Negated to HALT# Negated (Rerun)

57

0–0–0–

ns

BGACK# Negated to Bus Driven

58 (10)

1–1–1–

Clks

BG# Negated to Bus Driven

59 (10)

1–1–1–

Clks