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WED2CG472512V10D2 Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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WED2CG472512V10D2 Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 10 page WED2CG472512V-D2 6 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs Aug. 2002 Rev. B White Electronic Designs Corp. reserves the right to change products or specifications without notice. ADVANCED READ CYCLE TIMING PARAMETERS WRITE CYCLE TIMING PARAMETERS Description Sym 9ns 10ns 12ns 15ns Units Min Max Min Max Min Max Min Max Frequency fMAX 100 836750 MHz Clock Cycle Time tKHKH 10 12 15 20 ns Clock High Time tKHKL 4556 ns Clock Low Time tKLKH 4556 ns Clock to Output Valid tKHQV 9 101215 ns Clock to Output Invalid tKHQX1 3333 ns Clock to Output Low-Z tKHQX 4444 ns Output Enable to Output Valid tGLQV 4555 ns Output Enable to Output Low-Z tGLQX 0000 ns Output Enable to Output High-Z tGHQZ 4555 ns Address Setup tAVKH 2.5 2.5 2.5 2.5 ns Bank Enable Setup tEVKH 2.5 2.5 2.5 2.5 ns Address Hold tKHAX 1.0 1.0 1.0 1.0 ns Bank Enable Hold tKHEX 1.0 1.0 1.0 1.0 ns Description Sym 9ns 10ns 12ns 15ns Units Min Max Min Max Min Max Min Max Frequency fMAX 100 83 67 50 MHz Clock Cycle Time tKHKH 12 12 15 20 ns Clock High Time tKHKL 4556 ns Clock Low Time tKLKH 4556 ns Address Setup tAVKH 2.5 2.5 2.5 2.5 ns Address Hold tKHAX 1.0 1.0 1.0 1.0 ns Bank Enable Setup tEVKH 2.5 2.5 2.5 2.5 ns Bank Enable Hold tKHEX 1.0 1.0 1.0 1.0 ns Global Write Enable Setup tWVKH 2.5 2.5 2.5 2.5 ns Global Write Enable Hold tKHWX 1.0 1.0 1.0 1.0 ns Data Setup tDVKH 2.5 2.5 2.5 2.5 ns Data Hold tKHDX 1.0 1.0 1.0 1.0 ns |
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