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WED2ZL361MV50BC Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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WED2ZL361MV50BC Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
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1 / 12 page  1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED2ZL361MV June 2004 Rev. 3 DESCRIPTION The WEDC SyncBurst — SRAM family employs high- speed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18 SRAMs into a single BGA package to provide 1M x 36 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied “High or Low.” Asynchronous inputs include the sleep mode enable (ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. 1Mx36 Synchronous Pipeline Burst NBL SRAM FIGURE 1 – PIN CONFIGURATION Block Diagram Address Bus (SA0 - SA19) DQa, DQb DQPa, DQPb DQc, DQd DQPc, DQPd DQa - DQd DQPa - DQPd 1M x 18 1M x 18 CLK CKE# ADV# LBO# CS1# CS2 CS2# OE# WE# ZZ CLK CKE# ADV# LBO# CS1# CS2 CS2# OE# WE# ZZ CLK CKE# ADV# LBO# CE1# CE2 CE2# OE# WE# ZZ FEATURES Fast clock speed: 166, 150, 133, and 100MHz Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Single +3.3V ± 5% power supply (VCC) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging: • 119-bump BGA package Low capacitive bus loading This product is subject to change without notice. 1234567 A VCC SA SA SA SA SA VCC B SA CE2 SA ADV# SA CE2# NC C NC SA SA VCC SA SA NC D DQC DQPC VSS NC VSS DQPB DQB E DQC DQC VSS CE1#VSS DQB DQB F VCC DQC VSS OE# VSS DQB VCC G DQC DQC BWC#SA BWB# DQB DQB H DQC DQC VSS WE# VSS DQB DQB J VCC VCC NC VCC NC VCC VCC K DQD DQD VSS CLK VSS DQA DQA L DQD DQD BWD#NC BWA#DQA DQA M VCC DQD VSS CKE# VSS DQA VCC N DQD DQD VSS SA1 VSS DQA DQA P DQD DQPD VSS SA0 VSS DQPA DQA R NC SA LBO VCC NC SA NC T NC NC SA SA SA NC ZZ U VCC NC NC NC NC NC VCC (Top View) |
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