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WED3C7410E16M450BH9M Datasheet(PDF) 11 Page - White Electronic Designs Corporation |
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WED3C7410E16M450BH9M Datasheet(HTML) 11 Page - White Electronic Designs Corporation |
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11 / 15 page  11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3C7410E16M-XBHX July 2004 Rev. 0 PRELIMINARY The AVCC and L2AVCC power signals are provided on the WED3C7410E16M-XBHX to provide power to the clock generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power supplied to the AVCC input signal should be filtered of any noise in the 500kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 6 using surface mount capacitors with minimum Effective Series Inductance (ESL) is recommended. Multiple small capacitors of equal value are recommended over a single large value capacitor. PLL POWER SUPPLY FILTERING FIGURE 6 – POWER SUPPLY FILTER CIRCUIT AVCC (or L2AVCC) 2.2 µF 2.2 µF GND Low ESL surface mount capacitors VCC 10 Ω The circuit should be placed as close as possible to the AVCC pin to minimize noise coupled from nearby circuits. An identical but separate circuit should be placed as close as possible to the L2AVCC pin. It is often possible to route directly from the capacitors to the AVCC pin, which is on the periphery of the 255 BGA footprint, without the inductance of vias. The L2AVCC pin may be more difficult to route but is proportionately less critical. |
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