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WED3C7558M350BI Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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WED3C7558M350BI Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 13 page 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3C7558M-XBX August 2002 Rev. 7 PACKAGE PINOUT LISTING (continued) Signal Name Pin Number Active I/O 2.0V (7) 3.3V (7) STMS B8 Input SYSCLK C9 — Input TA# H14 Low Input TBEN C2 High Input TBST# A14 Low I/O TCK C11 High Input TDI (6) A11 High Input TDO A12 High Output TEA# H13 Low Input TLBISYNC# C4 Low Input TMS (6) B11 High Input TRST# (6) C10 Low Input TS# J13 Low I/O TSIZ[0-2] A13, D10, B12 High Output TT[0-4] B13, A15, B16, C14, C15 High I/O WT D2 Low Output VCC (2) F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9 — — 2.0V 2.0V VOLDET (3) F3 Low Output — — NOTES: 1. These are test signals for factory use only and must be pulled up to OVCC for normal machine operation. 2. OVCC inputs supply power to the I/O drivers and VCC inputs supply power to the processor core. 3. Internally tied to GND in the BGA package to indicate to the power supply that a low-voltage processor is present. This signal is not a power supply pin. 4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVCC (Selects 3.3V Interface) or to GND (Selects 2.0V Interface). 5. Uses one of 15 existing no-connects in WEDC’s WED3C750A8M-200BX. 6. Internal pull up on die. 7. OVCC supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVCC supplies power to the L2 cache I/O interface (L2ADDR (0-16], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT) and the L2 control signals and the SSRAM power supplies; and VCC supplies power to the processor core and the PLL and DLL (after filtering to become AVCC and L2AVCC respectively). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL/L2VSEL pin configurations and the voltage supplied. For actual recommended value of Vin or supply voltages see Recommended Operating Conditions. 8. Uses one of 20 existing VCC pins in WEDC's WED3C750A8M-200BX, no board level design changes are necessary. For new designs of WED3C7558M-XBX refer to PLL power supply filtering. 9. L20VCC for future designs that will require 2.0V L2 cache power supply - compatible with existing design using WED3C750A8M-200BX. 10. To disable SSRAM TAP controllers without interfering with the normal operation of the devices, STCK should be tied low (GND) to prevent clocking the devices. 11. STDI and STMS are internally pulled up and may be left unconnected. Upon power-up the SSRAM devices will come up in a reset state which will not interfere with the operation of the device. |
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