6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WED3DL644V

August 2005

Rev. 6

Parameter

Symbol

Units

Min

Max

Min

Max

Min

Max

Clock Cycle Time1

CL = 3

7

1000

8

1000

10

1000

ns

CL = 2

7.5

1000

10

1000

12

1000

Clock to valid Output delay1,2

5.4

6

7

ns

Output Data Hold Time2

22

2

ns

Clock HIGH Pulse Width3

2.5

2.75

3

ns

Clock LOW Pulse Width3

2.5

2.75

3

ns

Input Setup Time3

22

2

ns

Input Hold Time3

11

1

ns

CK to Output Low-Z2

1.0

1

1.5

ns

CK to Output High-Z

5.4

6

7

ns

Row Active to Row Active Delay4

14

20

20

ns

RAS# to CAS# Delay4

15

20

20

ns

Row Precharge Time4

15

20

20

ns

Row Active Time4

37

120,000

50

120,000

50

120,000

ns

Row Cycle Time - Operation4

60

70

80

ns

Row Cycle Time - Auto Refresh4,8

66

70

80

ns

Last Data in to New Column Address Delay5

11

1

CK

Last Data in to Row Precharge5

22

2

CK

Last Data in to Burst Stop5

11

1

CK

Column Address to Column Address Delay6

1.0

1.0

1.5

CK

Data Out to High Impedance from Precharge

CL3

33

3

CK

CL2

22

2

SDRAM AC CHARACTERISTICS

NOTES:

1.

Parameters depend on programmed CAS# latency.

2.

3.

4.

The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up

to the next higher integer.

5.

Minimum delay is required to complete write.

6.

All devices allow every cycle column address changes.

7.

In case of row precharge interrupt, auto precharge and read burst stop.

8.