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WED3EG7233S202JD3 Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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WED3EG7233S202JD3 Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
5 / 11 page 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7233S-D3 -JD3 May, 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifications without notice. IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR266@CL=2.0 Max DDR266@CL=2.5 Max DDR200@CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. TBD 1845 1845 mA Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. TBD 2205 2205 mA Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) TBD 72 72 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. TBD 810 810 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) TBD 450 450 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. TBD 900 900 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. TBD 2250 2250 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. TBD 2115 2115 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) TBD 3015 3015 mA Self Refresh Current IDD6 CKE ≤ 0.2V TBD 72 72 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. TBD 4050 4050 mA |
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