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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WED3EG7233S-D3

-JD3

May, 2005

Rev. 0

ADVANCED

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Recommended operating conditions, 0°C

Includes DDR SDRAM component only

Parameter

Symbol

Conditions

DDR266@CL=2.0

Max

DDR266@CL=2.5

Max

DDR200@CL=2

Max

Units

Operating Current

One device bank; Active - Precharge;

and DQS inputs changing once per

clock cycle; Address and control

inputs changing once every two

cycles.

TBD

1845

1845

mA

Operating Current

One device bank; Active-Read-

and control inputs changing once per

clock cycle.

TBD

2205

2205

mA

Precharge Power-

Down Standby

Current

All device banks idle; Power-down

TBD

72

72

rnA

Idle Standby Current

CS# = High; All device banks idle;

and other control inputs changing

DQ, DQS and DM.

TBD

810

810

mA

Active Power-Down

Standby Current

One device bank active; Power-Down

TBD

450

450

mA

Active Standby

Current

CS# = High; CKE = High; One device

DQS inputs changing twice per clock

cycle; Address and other control

inputs changing once per clock cycle.

TBD

900

900

mA

Operating Current

Burst = 2; Reads; Continuous burst;

One device bank active; Address

and control inputs changing once

= 0mA.

TBD

2250

2250

mA

Operating Current

Burst = 2; Writes; Continuous burst;

One device bank active; Address

and control inputs changing once per

and DQS inputs changing once per

clock cycle.

TBD

2115

2115

rnA

Auto Refresh

Current

TBD

3015

3015

mA

Self Refresh Current

CKE

≤ 0.2V

TBD

72

72

mA

Operating Current

Four bank interleaving Reads (BL=4)

control inputs change only during

Active Read or Write commands.

TBD

4050

4050

mA