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WED7P256ATA7003I25 Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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WED7P256ATA7003I25 Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
5 / 15 page 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED7PxxxATA70xxI25 July 2005 Rev. 1 White Electronic Designs Corp. reserves the right to change products or specifications without notice. 3. TRUE IDE MODE The card can be configured in a True IDE. This card is configured in this mode only when the OE# input signal is asserted to GND by the host during power on . In this True IDE mode Attribute Registers are not accessible from the host. Only I/O operation to the task file and data register is allowed. If this card is configured during power on sequence, data register is accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set Feature Command to put the device in 8-bit mode. True IDE Mode Read I/O Function Mode CE2# CE1# A0~A2 DMACK# DIOR# DIOW# D8~D15 D0~D7 Invalid mode L L XXXX High-Z High-Z Standby mode H HXHX X High-Z High-Z PIO Data register access H L 0 H L H Odd byte even byte Multiword DMA Data register access H H X L L H Odd byte even byte Alternate status access L H 6H H L H High-Z Status out Other task file access H L 1~7H H L H High-Z Data Note: X → L or H True IDE Mode Write I/O Function Mode CE2# CE1# A0~A2 DMACK# DIOR# DIOW# D8~D15 D0~D7 Invalid mode L L XXXX Don’t care Don’t care Standby mode H HXHX X Don’t care Don’t care PIO Data register access H L 0 H H L Odd byte even byte Multiword DMA Data register access H H X L H L Odd byte even byte Control register access L H 6H H H L Don’t care Control in Other task file access H L 1~7H H H L Don’t care Data Note: X → L or H CARD SYSTEM PERFORMANCE ITEM PERFORMANCE Set up time (Reset to Ready) 250 ms (max.) Set up time (Power down to Ready) 5.5 ms (max.) Data transfer rate to / from host 16.6 M byte / s burst (max.), theoretically Sustained read transfer rate 6.5 M byte / s (max.), actually *1 Sustained write transfer rate 6.0 M byte / s (max.), actually *1 Command to DRQ (Sector Re ad at Ready state) 4 ms (max.) Command to DRQ (Sector Write at Ready state) 700 ms (max.) Data transfer cycle end to ready (Sector write) 2 ms (typ.), 200 ms (max.) Auto Power down time 1.5s (min.), 1.8s (typ.) Notes: 1. The actual transfer rate is measured under ATA PIO mode 4 with single cycle time as 120ns. |
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