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WED7P1G0ATA8003C25 Datasheet(PDF) 5 Page - White Electronic Designs Corporation

Part # WED7P1G0ATA8003C25
Description  32MB to 4GB Flash Card
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

WED7P1G0ATA8003C25 Datasheet(HTML) 5 Page - White Electronic Designs Corporation

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxATA80xxC25
July 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
AC CHARACTERISTICS:
Attribute Memory Read Timing Specification
Attribute Memory access time is defined as 300ns. Detailed timing specs are shown in Table below.
Speed Version
300 ns
Item
Symbol
IEEE Symbol
Min ns.
Max ns.
Read Cycle Time
tc(R)
tAVAV
300
Address Access Time
ta(A)
tAVQV
300
Card Enable Access Time
ta(CE)
tELQV
300
Output Enable Access Time
ta(OE)
tGLQV
150
Output Disable Time from CE
tdis(CE)
tEHQZ
100
Output Disable Time from OE
tdis(OE)
tGHQZ
100
Address Setup Time
tsu(A)
tAVGL
30
Output Enable Time from CE
ten(CE)
tELQNZ
5
Output Enable Time from OE
ten(OE)
tGLQNZ
5
Data Valid from Address Change
tv(A)
tAXQX
0
Note: All times are in nanoseconds. The CE# signal or both the OE# signal and the WE# signal must be de-asserted between consecutive cycle operations.
Configuration Register (Attribute Memory) Write Timing Specification
The Card Configuration write access time is defined as 250ns. Detailed timing specifications are shown in Table below.
Speed Version
250 ns
Item
Symbol
IEEE Symbol
Min ns
Max ns
Write Cycle Time
tc(W)
tAVAV
250
Write Pulse Width
tw(WE)
tWLWH
150
Address Setup Time
tsu(A)
tAVWL
30
Write Recovery Time
trec(WE)
tWMAX
30
Data Setup Time for WE
tsu(D-WEH)
tDVWH
80
Data Hold Time
th(D)
tWMDX
30
Note: All times are in nanoseconds.
Common Memory Read Timing Specification
Item
Symbol
IEEE Symbol
Min ns.
Max ns.
Output Enable Access Time
ta(OE)
tGLQV
125
Output Disable Time from OE
tdis(OE)
tGHQZ
100
Address Setup Time
tsu(A)
tAVGL
30
Address Hold Time
th(A)
tGHAX
20
CE Setup before OE
tsu(CE)
tELGL
0
CE Hold following OE
th(CE)
tGHEH
20
Wait Delay Falling from OE
tv(WT-OE)
tGLWTV
35
Data Setup for Wait Release
tv(WT)
tQVWTH
0
Wait Width Time
tw(WT)
tWTLWTH
350 (3000 for CF+)
Note: The maximum load on -WAIT# is 1 LSTTL with 50pF total load. All times are in nanoseconds. The WAIT# signal may be ignored if the OE# cycle to cycle time is greater than
the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12ps but is
intentionally less in this specification.


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