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WED416S16030C7SI Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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WED416S16030C7SI Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 26 page 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED416S16030A April 2006 Rev. 1 White Electronic Designs Corp. reserves the right to change products or specifications without notice. NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A12-A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. Must be a legal command as defined in the Current State Truth Table. CLOCK ENABLE (CKE0) TRUTH TABLE Current State CKE Command Action Notes Previous Cycle Current Cycle CE# RAS# CAS# WE# BA0,1 A0-9, A11-12 Self Refresh H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation L H L H H L X X ILLEGAL L H L H L X X X ILLEGAL L H L L X X X X ILLEGAL L L X X X X X X Maintain Self Refresh Power Down H X X X X X X X INVALID 1 L H H X X X X X Power Down Mode exit, all banks idle 2 L H L X X X X X ILLEGAL L L X X X X X X Maintain Power Down Mode All Banks Idle HH H X X X Refer to the Idle State section of the Current State Truth Table 3 HH L H X X HH L L H X H H L L L H X X CBR Refresh H H L L L L OP Code Mode Register Set 4 HL H X X X Refer to the Idle State section of the Current State Truth Table 3 HL L H X X HL L L H X H L L L L H X X Entry Self Refresh 4 H L L L L L OP Code Mode Register Set L X X X X X X X Power Down 4 Any State other than listed above HH X X X X X X Refer to the Operations in the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle 5 L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend |
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