WV3DG72256V-AD2

5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

January 2006

Rev. 0

AC OPERATING TEST CONDITIONS

Parameter

Value

Units

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall time

tr/tf = 1/1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig. 2

AC OPERATING TEST CONDITIONS

Parameter

Symbol

Value

Units

Notes

133/100

Row active to row active delay

15

ns

1

RAS# to CAS# delay

20

ns

1

Row Precharge time

20

ns

1

Row active time

45

ns

1

100

µs

Row cycle time

65

ns

1

Last data in to row precharge

2

CLK

2

Last data in to Active delay

—

Last data in to new col. address delay

1

CLK

1

Last data in to burst stop

1

CLK

2

Col. address to col. address delay

1

CLK

2

Number of valid output data

CAS Latency = 3

2

CLK

3

Cas Latency = 2

1

ea

4

Notes: 1. The minimum number of clock cycles is determined by driving the minimum time required with clock cycle time and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

3.3V

1220

870

Output

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

50pF

50

Output

50pF

Z0 = 50

PRELIMINARY*