WSE128K16-XXX

6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

PRELIMINARY

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

March 2005

Rev. 3

EEPROM WRITE

A write cycle is initiated when OE# is high and a low pulse

is on EWE# or ECS# with ECS# or EWE# low. The address

is latched on the falling edge of ECS# or EWE# whichever

occurs last. The data is latched by the rising edge of ECS#

or EWE#, whichever occurs first. A byte write operation

will automatically continue to completion.

WRITE CYCLE TIMING

Figures 7 and 8 show the write cycle timing relationships.

A write cycle begins with address application, write enable

and chip select. Chip select is accomplished by placing the

ECS# line low. Write enable consists of setting the EWE#

line low. The write cycle begins when the last of either

ECS# or EWE# goes low.

The EWE# line transition from high to low also initiates

an internal 150 µsec delay timer to permit page mode

operation. Each subsequent EWE# transition from high

to low that occurs before the completion of the 150 µsec

time out will restart the timer from zero. The operation of

the timer is the same as a retriggerable one-shot.

EEPROM AC WRITE CHARACTERISTICS

Write Cycle Parameter

Symbol

Min

Max

Unit

Write Cycle Time, TYP = 6ms

10

ms

Address Set-up Time

0ns

Write Pulse Width (EWE# or ECS#)

150

ns

Chip Select Set-up Time

0ns

Address Hold Time

100

ns

Data Hold Time

10

ns

Chip Select Hold Time

0ns

Data Set-up Time

100

ns

Output Enable Set-up Time

10

ns

Output Enable Hold Time

10

ns

Write Pulse Width High

50

ns