FLASH MEMORY

K8S6415ET(B)B

Revision 1.1

January, 2006

8

Table 4. Device Bus Operations

Operation

CE

OE

WE

A16-21

A/DQ0-15

RESET

CLK

AVD

Asynchronous Read Operation

L

L

H

Add In

Add In/

HL

L

Write

L

H

Add In

HL

X

Standby

H

X

XX

High-Z

H

XX

Hardware Reset

X

X

XX

High-Z

L

XX

Load Initial Burst Address

L

H

H

Add In

Add In

H

Burst Read Operation

L

L

H

X

Burst

HH

Terminate Burst Read Cycle via CE

H

X

XX

High-Z

H

XX

Terminate Burst Read Cycle via RESET

X

X

XX

High-Z

L

XX

Terminate Current Burst Read Cycle and Start

New Burst Read Cycle

L

H

H

Add In

Add In

H

PRODUCT INTRODUCTION

The K8S6415E is an 64Mbit (67,108,364 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply

operating within the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mecha-

nism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To pro-

vide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into

135 blocks (32-Kword x 127 , 4-Kword x 8, ). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks

can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the pro-

grammed data, 135 memory blocks can be hardware protected. Regarding read access time, at 54MHz, the K8S6415E provides a

burst access of 14.5ns with initial access times of 90ns at 30pF. At 66MHz, the K8S6415E provides a burst access of 11ns with initial

access times of 70ns at 30pF. The command set of K8S6415E is compatible with standard Flash devices. The device uses Chip

Enable (CE), Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For

burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective com-

mand codes. The command codes to be combined with addresses and data are sequentially written to the command registers using

microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase cir-

cuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The

K8S6415E is implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/

Erase Routines are invoked by program/erase command sequences. The Internal Program Routine automatically programs and ver-

ifies data at specified address. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and

then executes the erase operation. The K8S6415E has means to indicate the status of completion of program/erase operations. The

status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device auto-

matically resets itself to the read mode. The device requires only 25 mA as burst and asynchronous mode read current and 15 mA

for program/erase operations.