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AS7C1026A-15JI Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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AS7C1026A-15JI Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 9 page ® AS7C1026A AS7C31026A 2/6/01; V.0.9 Alliance Semiconductor P. 2 of 9 Functional description The AS7C1026A and AS7C31026A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 65,536 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high-performance applications. When CE is high the devices enter standby mode. The AS7C1026A is guaranteed not to exceed 55 mW power consumption in CMOS standby mode. The devices also offer 2.0V data retention. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026A) or 3.3V supply (AS7C31026A). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm × 6 mm. Absolute maximum ratings Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table Key: H = High, L = Low, X = don’t care. Parameter Symbol Min Max Unit Voltage on VCC relative to GND AS7C1026A Vt1 –0.50 +7.0 V AS7C31026A Vt1 –0.50 +5.0 V Voltage on any pin relative to GND Both Vt2 –0.50 VCC +0.50 V Power dissipation Both PD –1.0 W Storage temperature (plastic) Both Tstg –65 +150 °C Ambient temperature with VCC applied Both Tbias –55 +125 °C DC current into outputs (low) Both IOUT –20 mA CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode H X X X X High Z High Z Standby (ISB), ISBI) LHL L H DOUT High Z Read I/O0–I/O7 (ICC) LHL H L High Z DOUT Read I/O8–I/O15 (ICC) LHL L L DOUT DOUT Read I/O0–I/O15 (ICC) LL X L L DIN DIN Write I/O0–I/O15 (ICC) LL X L H DIN High Z Write I/O0–I/O7 (ICC) LL X H L High Z DIN Write I/O8–I/O15 (ICC) L L H X H X X H X H High Z High Z Output disable (ICC) |
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