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TLE6266G Datasheet(PDF) 11 Page - Infineon Technologies AG

Part # TLE6266G
Description  System Basis Chip
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE6266G Datasheet(HTML) 11 Page - Infineon Technologies AG

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Target Datasheet TLE 6266
Version 1.06
12
2002-11-26
bus lines is affected by a bus line failure) the EME performance of the system is
degraded from the differential mode.
Figure 5
Testing the Bus Connection in Receive-only Mode
6.3
Bus Failure Management
There are 9 different CAN bus wiring failures defined by the ISO 11519-2 standard.
These failures are devided into 7 failure groups (see Table 4). When a bus wiring failure
is detected the device automatically switches to a dedicated CANH or CANL single-wire
mode to maintain the communication if necessary. Therefore it is equipped with one
differential receiver and four single ended comparators (two for each bus line).
To avoid false triggering by external RF influences, the single wire modes are activated
after a certain delay time. As soon as the bus failure disappears the transceiver switches
back to differential mode after another time delay.
The bus failures are monitored via the diagnosis protocoll of the SPI. Therefore it is
possible to distinguish 6 CAN bus failures or failure groups on the SPI output bits 8 to 13
(see Table 4 and 5). The failures are reported until transmission of the next CAN word
begins.The SPI output bit 0 for CAN bus wiring failure can be read out without SPI
transmission directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal
from LOW to HIGH resets the SPI diagnosis bit 0.
The differential receiver threshold is set to typ. -2.5V. This ensures correct reception in
the normal operation mode as well as in the failure cases 1, 2, 3a and 4 with a noise
margin as high as possible. When one of the bus failures 3, 5, 6, 6a, and 7 is detected,
the defective bus wire is disabled by switching off the affected bus termination and output
stage. Simultaneously the multiplexing output of the receiver circuit is switched to the
unaffected single ended comparator.
1
2
5
4
3


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