RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
ii
Track ID: JATR-1076-21 Rev. 1.21
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©2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
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means without the written permission of Realtek Semiconductor Corp.
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technical inaccuracies or typographical errors.
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USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
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REVISION HISTORY
Revision
Release Date
Summary
1.0
2003/06/09
First release.
1.1
2003/09/26
Minor cosmetic changes.
Modify LED Pin behavior.
1.2
2004/01/20
Add LED multi-mode definition (7.5 LED and PHY Address
Configuration, page 19).
Add Power dissipation info (Table 31).
Bit <0:8> default setting changed to 0 (Table 9).
Bit <0:13> default setting changed to 0 (Table 9).
Bit <5:7> default setting changed to 0 (Table 14).
Bit <17:5> default setting changed to 1 (Table 17).
Bit <25:0> default setting changed to 0 (Table 20).
Bit <25:1> default setting changed to 0 (Table 20).
Bit <25:11~7> default setting changed to 00001 (Table 20).
1.21
2004/10/12
Package additions. See section 10, Ordering Information, page 33.
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