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RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
25
Track ID: JATR-1076-21 Rev. 1.21
TXCLK
TXEN
TXD[0:3]
CRS
TPTX+-
t 6
t8
t
t9
7
Figure 7. MII Transmission Cycle Timing-2
8.2.2.
MII Reception Cycle Timing
Table 34. MII Reception Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
100Mbps
14
20
26
ns
t1
RXCLK high pulse width
10Mbps
140
200
260
ns
100Mbps
14
20
26
ns
t2
RXCLK low pulse width
10Mbps
140
200
260
ns
100Mbps
40
ns
t3
RXCLK period
10Mbps
400
ns
100Mbps
10
ns
t4
RXER, RXDV, RXD[0:3] setup to
RXCLK rising edge
10Mbps
6
ns
100Mbps
10
ns
t5
RXER, RXDV, RXD[0:3] hold
after RXCLK rising edge
10Mbps
6
ns
100Mbps
130
ns
t6
Receive frame to CRS high
10Mbps
600
ns
100Mbps
240
ns
t7
End of receive frame to CRS low
10Mbps
600
ns
100Mbps
150
ns
t8
Receive frame to sampled edge of
RXDV
10Mbps
3200
ns
100Mbps
120
ns
t9
End of receive frame to sampled
edge of RXDV
10Mbps
800
ns
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