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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet

Rev. 03 — 12 November 2004

9 of 21

Philips Semiconductors

74HC73

Dual JK flip-flop with reset; negative-edge trigger

11. Dynamic characteristics

Table 8:

Dynamic characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

see Figure 6

-

52

160

ns

-

19

32

ns

-

15

27

ns

-

16

-

ns

propagation delay nCP to nQ

see Figure 6

-

52

160

ns

-

19

32

ns

-

15

27

ns

-

16

-

ns

propagation delay nR to nQ, nQ

see Figure 7

-

50

145

ns

-

18

29

ns

-

14

25

ns

-

15

-

ns

output transition time

see Figure 6

-

19

75

ns

-

7

15

ns

-

6

13

ns

nCP clock pulse width HIGH or LOW

see Figure 6

80

22

-

ns

16

8

-

ns

14

6

-

ns

nR reset pulse width HIGH or LOW

see Figure 7

80

22

-

ns

16

8

-

ns

14

6

-

ns

removal time nR to nCP

see Figure 7

80

22

-

ns

16

8

-

ns

14

6

-

ns

set-up time nJ, nK to nCP

see Figure 6

80

22

-

ns

16

8

-

ns

14

6

-

ns