Device Operation

The CLC020 SMPTE 259M Digital Video Serializer is used in

digital video signal origination and processing equipment:

cameras, video tape recorders, telecines, video test equip-

ment and others. It converts parallel component or compos-

ite digital video signals into serial format. Logic levels within

this equipment are normally TTL-compatible as produced by

CMOS or bipolar logic devices. The encoder outputs ECL-

compatible serial digital video (SDV) signals conforming to

SMPTE 259M-1997. The CLC020 operates at all standard

SMPTE and ITU-R parallel data rates.

VIDEO DATA PROCESSING CIRCUITS

The input data register accepts 8 or 10-bit parallel data and

clock signals having CMOS/TTL-compatible signal levels.

Parallel data may conform to any of several standards:

SMPTE 125M, SMPTE 267M, SMPTE 244M or ITU-R

BT.601. If data is 8-bit, it is converted to a 10-bit represen-

tation according to the type of data being input: component

4:2:2 per SMPTE 259M paragraph 7.1.1, composite NTSC

per paragraph 8.1.1 or composite PAL per paragraph 9.1.1.

Output from this register feeds the SMPTE polynomial

generator/serializer and sync detector. All CMOS inputs in-

cluding the P

The sync detector or TRS character detector accepts data

from the input register. The detection function is controlled

by Sync Detect Enable, a low-true, TTL-compatible, external

signal. Synchronization words, the timing reference signals

(TRS), start-of-active-video (SAV) and end-of-active-video

(EAV) are defined in SMPTE 125M-1995 and 244M. The

sync detector supplies control signals to the SMPTE polyno-

mial generator that identify the presence of valid video data.

The sync detector performs input TRS character LSB-

clipping as prescribed in ITU-R-BT.601. LSB-clipping causes

all TRS characters with a value between 000h and 003h to

be forced to 000h and all TRS characters with a value

between 3FCh and 3FFh to be forced to 3FFh. Clipping is

done prior to encoding.

The SMPTE polynomial generator accepts the parallel

video data and encodes it using the polynomial X

specified in SMPTE 259M–1997, paragraph 5 and Annex C.

The scrambled data is then serialized for output.

The NRZ-to-NRZI converter accepts serial NRZ data from

the SMPTE polynomial genertor and converts it to NRZI

using the polynomialX+1per SMPTE 259M–1997, para-

graph 5.2 and Annex C. The transmission bit order is LSB

first, per paragraph 6. The converter’s output feeds the

output driver amplifier.

PHASE-LOCKED LOOP AND VCO

The phase-locked loop (PLL) system generates the output

serial data clock at 10x the parallel data clock frequency.

This system consists of a VCO, divider chain, phase-

frequency detector and internal loop filter. The VCO free-

running frequency is internally set. The PLL automatically

generates the appropriate frequency for the serial clock rate

using the parallel data clock (P

ence. Loop filtering is internal to the CLC020. The VCO has

separate V

16, which may be supplied power independently via an

external low-pass filter, if desired. The PLL acquisition (lock)

LOCK DETECT

The Lock Detect output of the phase-frequency detector

indicates the PLL lock condition. It is a logic HIGH when the

loop is locked. The output is CMOS/TTL-compatible and is

suitable for driving other CMOS devices or a LED indicator.

SERIAL DATA OUTPUT BUFFER

The current-mode serial data outputs provide low-skew

complimentary or differential signals. The output buffer de-

sign can drive 75

Ω coaxial cables (AC-coupled) or 10k/100k

ECL/PECL-compatible devices (DC-coupled). Output levels

are 800 mV

Ω AC-coupled, back-matched

loads. The output level is 400 mV

P-P

coupled into 75

Ω (See Application Information for details).

The 75

Ω resistors connected to the SDO outputs are back-

matching resistors. No series back-matching resistors

should be used. SDO output levels are controlled by the

value of R

normally 1.69 k

device is in an out-of-lock condition. Separate V

V

serial output driver.

POWER-ON RESET

The CLC020 has an internally controlled, automatic,

power-on reset circuit. This circuit clears TRS detection

circuitry, all latches, registers, counters and polynomial gen-

erators and disables the serial output. The SDO outputs are

tri-stated during power-on reset. The part will remain in the

reset condition until the parallel input clock is applied.

It is recommended that P

30 µs after power has reached V

10091714

FIGURE 4. Power-On Reset Sequence

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