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CLC020BCQ Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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CLC020BCQ Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 15 page Device Operation (Continued) BUILT-IN SELF-TEST (BIST) The CLC020 has a built-in self-test (BIST) function. The BIST performs a comprehensive go-no-go test of the device. The test uses either a full-field color bar for NTSC or a PLL pathological for PAL as the test data pattern. Data is input internally to the input data register, processed through the device and tested for errors. Table 1 gives device pin func- tions and Table 2 gives the test pattern codes used for this function. The signal level at Test_Output, pin 26, indicates a pass or fail condition. The BIST is initiated by applying the code for the desired BIST to D0 throught D3 (D9 through D4 are 00h) and a 27 MHz clock at the P CLK input. Since all parallel data inputs are equipped with an internal pull-down device, only those inputs D0 through D3 which require a logic-1 need be pulled high. After the Lock_Detect output goes high (true) indicating the VCO is locked on frequency, TPG_Enable, pin 17, is then taken to a logic high. TPG_Enable may be temporarily con- nected to the Lock_Detect output to automate BIST opera- tion. Test_Output, pin 26, is monitored for a pass/fail indica- tion. If no errors have been detected, this output will go to a logic high level approximately 2 field intervals after TPG_Enable is taken high. If errors have been detected in the internal circuitry of the CLC020, Test_Output will remain low until the test is terminated. The BIST is terminated by taking TPG_Enable to a logic low. Continuous serial data output is available during the test. TEST PATTERN GENERATOR The CLC020 features an on-board test pattern generator (TPG). Four full-field component video test patterns for both NTSC and PAL standards, and 4x3 and 16x9 raster sizes are produced. The test patterns are: flat-field black, PLL patho- logical, equalizer (EQ) pathological and a modified 75%, 8-color vertical bar pattern. The pathologicals follow recom- mendations contained in SMPTE RP 178–1996 regarding the test data used. The color bar pattern does not incorpo- rate bandwidth limiting coding in the chroma and luma data when transitioning between the bars. For this reason, it may not be suitable for use as a visual test pattern or for input to video D-to-A conversion devices unless measures are taken to restrict the production of out-of-band frequency compo- nents. The TPG is operated by applying the code for the desired test pattern to D0 through D3 (D4 through D9 are 00h). Since all parallel data inputs are equipped with an internal pull- down device, only those inputs D0 through D3 which require a logic-1 need be pulled high. Next, apply a 27 or 36 MHz signal, appropriate to the raster size desired, at the P CLK input and wait until the Lock_Detect output goes true indi- cating the VCO is locked on-frequency. Then, take TPG_Enable, pin 17, to a logic high. The serial test pattern data appears on the SDO outputs. TPG_Enable may be temporarily connected to the Lock_Detect output to auto- mate TPG operation. The TPG mode is exited by taking TPG_Enable to a logic low. Table 1 gives device pin func- tions for this mode. Table 2 gives the available test patterns and selection codes. 10091706 FIGURE 5. Built-In Self-Test Control Sequence www.national.com 7 |
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