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CLC020BCQ Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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CLC020BCQ Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 15 page  Application Information A typical application circuit for the CLC020 is shown in Figure 7. This circuit demonstrates the capabilities of the CLC020 and allows its evaluation in a variety of configura- tions. An assembled demonstration board with more com- prehensive evaluation options is available, part number SD020EVK. The board may be ordered through any of Na- tional’s sales offices. Complete circuit board layouts and schematics, for the SD020EVK are available on National’s WEB site in the application information for this device. For latest information, please see: www.national.com/appinfo/ interface APPLICATION CIRCUIT Several different input and output drive and loading options can be constructed on the SD020EVK application circuit board, Figure 8. Pin headers are provided for input cabling and control signal access. The appropriate value resistor packs, 220 and 330 Ω for TTL or 50Ω for signal sources requiring such loading, should be installed at RP1-4 before applying input signals. The board’s outputs may be DC interfaced to PECL inputs by first installing 124 Ω resistors at R1B and R2B, changing R1A and R2A to 187 Ω and replacing C1 and C2 with short circuits. The PECL inputs should be directly connected to J1 and J2 without cabling. If 75 Ω cabling is used to connect the CLC020 to the PECL inputs, the voltage dividers used on the CLC020 outputs must be removed and re-installed on the circuit board where the PECL device is mounted. This will provide correct termination for the cable and biasing for both the CLC020’s outputs and the PECL inputs. It is most impor- tant to note that a 75 Ω or equivalent DC loading (measured with respect to the negative supply rail) must always be installed at both of the CLC020’s SDO outputs to obtain proper signal levels from device. When using 75 Ω Thevenin- equivalent load circuits, the DC bias applied to the SDO outputs should not exceed +3V with respect to the negative supply rail. Serial output levels should be reduced to 400 mV p-p by changing RREF to 3.4 k Ω. The Test Out output is intended for monitoring by equipment presenting high impedance loading (>500 Ω). When monitor- ing the Lock Detect output, the attached monitoring circuit should present a DC resistance greater than 5 k Ω so that Lock Detect indicator operation is not affected. 10091708 FIGURE 7. Typical Application Circuit www.national.com 10 |
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Similar Description - CLC020BCQ |
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