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74LV10PWDH Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LV10PWDH Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 10 page Philips Semiconductors Product specification 74LV10 Triple 3-input NAND gate 1998 Apr 20 3 PIN CONFIGURATION SV00416 1 2 3 4 5 6 7 1A 1B 2A 2B 2C 2Y GND V CC 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9 8 LOGIC SYMBOL (IEEE/IEC) 5 SV00418 1 2 12 4 6 8 9 10 11 13 & & & 3 LOGIC SYMBOL 1C 1A 13 1 1B 2 2C 2A 5 3 2B 4 3C 3A 11 9 3B 10 SV00417 2Y 3Y 6 8 12 1Y LOGIC DIAGRAM (ONE GATE) SV00419 A B C Y RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT VCC DC supply voltage See Note1 1.0 3.3 3.6 V VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V Tamb Operating ambient temperature range in free air See DC and AC characteristics –40 –40 +85 +125 °C tr, tf Input rise and fall times VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V – – – – – – 500 200 100 ns/V NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. |
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