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IDT72V70810TF Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT72V70810TF Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 22 page 11 COMMERCIALTEMPERATURERANGE IDT72V70810 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS NOTE: 1. n denotes an input stream number from 0 to 7. Name(1) Description OFn2, OFn1, OFn0 These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to (Offset Bits 2, 1 & 0) start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the F0i input of the device. See Figure 5. DLEn (Data Latch Edge) ST-BUS® mode: DLEn = 0, if clock rising edge is at the ¾ point of the bit cell. DLEn = 1, if when clock falling edge is at the ¾ of the bit cell. GCI mode: DLEn = 0, if clock falling edge is at the ¾ point of the bit cell. DLEn = 1, if when clock rising edge is at the ¾ of the bit cell. Read/Write Address: 03H for FOR0 register, 04H for FOR1 register, Reset Value: 0000H for all FOR registers. 15 14 13 12 11 10 9876543210 OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0 FOR0 Register 15 14 13 12 11 10 9876543210 OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4 FOR1 Register |
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