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74LV174D Datasheet(PDF) 7 Page - NXP Semiconductors |
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74LV174D Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 14 page Philips Semiconductors Product specification 74LV174 Hex D-type flip-flop with reset; positive edge-trigger 1998 May 20 7 AC CHARACTERISTICS (Continued) GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM CONDITION LIMITS –40 to +85 °C LIMITS –40 to +125 °C UNIT VCC(V) MIN TYP1 MAX MIN MAX 1.2 – –10 – – – Hold time 2.0 5 –4 – 5 – th Hold time Dn to CP Figure 3 2.7 5 –2 – 5 – ns Dn to CP 3.0 to 3.6 5 –22 – 5 – 4.5 to 5.5 5 –13 5 2.0 14 40 – 12 – f Maximum clock Figure 1 2.7 19 58 – 16 – MHz fmax pulse frequency Figure 1 3.0 to 3.6 24 702 – 20 – MHz 4.5 to 5.5 36 1003 30 NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. AC WAVEFORMS VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. tPLH tPHL 1/fmax VOH Qn OUTPUT VI CP INPUT GND VOL VM VM tw SV00351 Figure 1. The clock (CP) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency. Vi VOL VM tw trem tPHL VM Qn OUTPUT CP INPUT GND VOH MR INPUT Vi GND SV00352 VM Figure 2. The master reset (MR) pulse width, the master reset to output (Qn) propagation delay and the master reset to clock removal time. |
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