ADM1064ACP datasheet(5/32 Pages) AD

Part #	ADM1064ACP

Description	Super Sequencer with Voltage Readback ADC

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ADM1064

Rev. 0 | Page 5 of 32

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Input Reference Voltage on REFIN Pin,

VREFIN

2.048

V

Resolution

12

Bits

INL

±2.5

LSB

Endpoint corrected, VREFIN = 2.048 V

Gain Error

±0.05

%

VREFIN = 2.048 V

Conversion Time

0.44

ms

One conversion on one channel

84

ms

All 12 channels selected, 16x averaging enabled

Offset Error

±2

LSB

VREFIN = 2.048 V

Input Noise

0.25

LSBrms

Direct input (no attenuator)

REFERENCE OUTPUT

Reference Output Voltage

2.043

2.048

2.053

V

No load

Load Regulation

−0.25

mV

Sourcing current, IDACnMAX = −100 µA

0.25

mV

Sinking current, IDACnMAX = 100 µA

Minimum Load Capacitance

1

µF

Capacitor required for decoupling, stability

Load Regulation

2

mV

Per 100 µA

PSRR

60

dB

DC

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1–6)

Output Impedance

500

kΩ

VOH

11

12.5

14

V

IOH = 0

10.5

12

13.5

V

IOH = 1µA

IOUTAVG

20

µA

2 V < VOH < 7 V

Standard (Digital Output) Mode (PDO1–10)

VOH

2.4

V

VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA

4.5

V

VPU to Vpn = 6.0 V, IOH = 0 mA

VPU − 0.3

V

VPU ≤ 2.7 V, IOH = 0.5 mA

VOL

0

0.50

V

IOL = 20 mA

IOL2

20

mA

Maximum sink current per PDO pin

ISINK 2

60

mA

Maximum total sink for all PDOs

RPULL-UP

20

kΩ

Internal pull-up

ISOURCE (VPn)2

2

mA

Current load on any VPn pull-ups, that is, total

source current available through any number of

PDO pull-up switches configured onto any one

Three-State Output Leakage Current

10

µA

VPDO = 14.4 V

Oscillator Frequency

90

100

110

kHz

All on-chip time delays derived from this clock

DIGITAL INPUTS (VXn, A0, A1)

Input High Voltage, VIH

2.0

V

Maximum VIN = 5.5 V

Input Low Voltage, VIL

0.8

V

Maximum VIN = 5.5 V

Input High Current, IIH

−1

µA

VIN = 5.5 V

Input Low Current, IIL

1

µA

VIN = 0

Input Capacitance

5

pF

Programmable Pull-Down Current,

IPULL-DOWN

20

µA

VDDCAP = 4.75, TA = 25°C, if known logic state is

required

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH

2.0

V

Input Low Voltage, VIL

0.8

V

Output Low Voltage, VOL2

0.4

V

IOUT = −3.0 mA

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