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TMS320C209PN57 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320C209PN57 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 83 page  TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C209 Terminal Functions (Continued) TERMINAL TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) WE 62 O/Z Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15–D0). Data can be latched by an external device on the rising edge of WE. WE is active on all external program, data, and I/O writes. WE goes into the high-impedance state when OFF is active low. RAMEN 37 I RAM enable. RAMEN enables the 4K × 16 words of on-chip RAM. MULTIPROCESSING SIGNALS BR 68 O/Z Bus-request signal. BR is asserted during access of external global data-memory space. BR can be used to extend the data memory address space by up to 32K words. BR goes into the high-impedance state when OFF is active low. BIO 9 I Branch control input. BIO is polled by BIOZ instruction. If BIO is low, the TMS320C209 executes a branch. If BIO is not used, it should be pulled high. XF 75 O/Z External flag output (latched software-programmable signal). XF is used for signaling other processors in multiprocessing configurations or as a general-purpose output pin. IACK 79 O/Z Interrupt-acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is active low. INITIALIZATION, INTERRUPT, AND RESET OPERATIONS INT1 INT2 INT3 33 34 35 I External-user interrupts. INT1–INT3 are prioritized and maskable by the interrupt-mask register and the interrupt-mode bit. If INT1–INT3 are not used, they should be pulled high. NMI 36 I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked through the INTM or the IMR. When NMI is activated, the processor traps to the appropriate vector location. If NMI is not used, it should be pulled high. RS RS 4 6 I Reset input. RS and RS cause the TMS320C209 to terminate execution and force the program counter to 0. When RS is brought high, execution begins at location 0 of program memory after 16 cycles. RS affects various registers and status bits. MP/MC 10 I Microprocessor/microcontroller-mode-select pin. If MP/MC is low, the on-chip ROM is mapped into program space. When MP/MC is high, the device accesses off-chip memory. OSCILLATOR/TIMER SIGNALS CLKIN1/2 CLKOUT1 77 O/Z Master clock output signal. CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the rising edges of CLKOUT1. CLKOUT1 goes into the high-impedance state when OFF is active low. CLKMOD 74 I Clock-input mode. CLKMOD (when high) enables the clock doubler and phase-locked loop (PLL) on the clock input signal. If the internal oscillator is not used, X1 should be left unconnected. CLKIN/X2 X1 69 70 I O Input clock. CLKIN/X2 is the input clock to the device. As CLKIN, the pin operates as the external oscillator clock input, and as X2, the pin operates as the internal oscillator input with X1 being the internal oscillator output. TOUT 72 O Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT1-cycle wide. PLL5V 38 I PLL operating at 5 V. When PLL5V is operating at 5 V, PLL5V should be strapped high. RES1 40 I Reserved input pin. Do not connect to RES1. † I = input, O = output, Z = high impedance, PWR = power, GND = ground |
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