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74LVCH162374ADGG Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVCH162374ADGG Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 1999 Aug 05 3 Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 30 Ω series termination resistors; 5 V input/output tolerant; 3-state 74LVC162374A; 74LVCH162374A QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns. Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. ORDERING INFORMATION PINNING SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay CP to Qn CL = 50 pF; VCC = 3.3 V 3.8 ns fmax maximum clock frequency 150 MHz CI input capacitance 5.0 pF CPD power dissipation capacitance per flip-flop VCC = 3.3 V; note 1 30 pF OUTSIDE NORTH AMERICA NORTH AMERICA PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC162374ADL VC162374A DL −40 to +85 °C 48 SSOP plastic SOT370-1 74LVC162374ADGG VC162374A DGG 48 TSSOP plastic SOT362-1 74LVCH162374ADL VCH162374A DL 48 SSOP plastic SOT370-1 74LVCH162374ADGG VCH162374A DGG 48 TSSOP plastic SOT362-1 PIN SYMBOL DESCRIPTION 11OE output enable input (active LOW) 2, 3, 5, 6, 8, 9, 11, 12 1Q0 to 1Q7 3-state flip-flop outputs 4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V) 7, 18, 31, 42 VCC DC supply voltage 13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7 3-state flip-flop outputs 24 2OE output enable input (active LOW) 25 2CP clock input 36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7 data inputs 48 1CP clock input |
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