6.42

IDT707288S/L

High-Speed 64K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

8

NOTES:

1 . Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second 16Kx16

memory spaces, Bank 2 to the third 16Kx16 memory spaces, and Bank 3

to the fourth 16Kx16 memory spaces. 'LEFT' indicates the bank is assigned

to the left port; 'RIGHT' indicates the bank is assigned to the right port. 0-4 banks

may be assigned to either port.

tri-statable. When changing the bank assignments, accesses of the affected

banks must be suspended. Accesses may continue uninterrupted in banks that

are not beign reallocated.

Assigning the Banks via the

External Bank Selects

TherearefourbankselectpinsavailableontheIDT707288, andeach

of these pins is associated with a specific bank within the memory array.

The pins are user-controlled inputs: access to a specific bank is assigned

toaparticularportby settingtheinputtotheappropriatelevel.Theprocess

ofassigningthebanksisdetailedinTruthTableIV.Onceabankisassigned

toaport,theowningporthasfullaccesstoreadandwritewithinthatbank.

Theoppositeportisunabletoaccessthatbankuntiltheuserreassignsthe

port.Accessbyaporttoabankwhichitdoesnotcontrolwillhavenoeffect

Truth Table IV – Memory Bank

Mailbox Interrupts and Interrupt

Control Registers

Iftheuserchoosesthemailboxinterruptfunction,fourmailboxlocations

are assigned to each port. These mailbox locations are external to the

memory array. The mailboxes are accessed by setting

while holding

The mailboxes are 16 bits wide and controllable by byte: the message

isuser-definedsincetheseareaddressableSRAMlocations.Aninterrupt

is generated to the opposite port upon writing to the upper byte of any

mailbox location. A port can read the message it has just written in order

toverifyit:thisread willnotalterthestatusoftheinterruptsenttotheopposite

port.Theinterruptedportcancleartheinterruptbyreadingtheupperbyte

oftheapplicablemailbox.Thisreadwillnotalterthecontentsofthemailbox.

The use of mailboxes to generate interrupts to the opposite port and the

reading of mailboxes to clear interrupts is detailed in Truth Table V.

Ifdesired,anyofthemailboxinterruptscanbeindependentlymasked

viasoftware.MaskingoftheinterruptsourcesisdoneintheMaskRegister.

The masks are individual and independent: a port can mask any

combinationofinterruptsourceswithnoeffectontheothersources.Each

port can modify only its own Mask Register. The use of this register is

detailed in Truth Table V.

Tworegistersareprovidedtopermitinterpretationofinterrupts:these

are the Interrupt Cause Register and the Interrupt Status Register. The

Interrupt Cause Register gives the user a snapshot of what has caused

theinterrupttobegenerated-thespecificmailboxwrittentobytheopposite

port.Theinformationinthisregisterprovidespost-masksignals:interrupt

sources that have been masked will not be updated. The Interrupt Status

Registergivestheuserthestatusofallbitsthatcouldpotentiallycausean

interrupt regardless of whether they have been masked. The use of the

Interrupt Cause Register and the Interrupt Status Register is detailed in

Truth Table V.

port can be assigned as many banks within the array as needed, up to

and including all four banks.

arenottri-statable.Whenchangingthebankassignments,accessesofthe

affectedbanksmustbesuspended.Accessesmaycontinueuninterrupted

in banks that are not being reallocated.

BKSEL0

BKSEL1

BKSEL2

BKSEL3

BANK AND

HX

X

X

BANK 0 LEFT

XH

X

X

BANK 1 LEFT

XX

H

X

BANK 2 LEFT

XXX

H

BANK 3 LEFT

L

X

X

X

BANK 0 RIGHT

X

L

X

X

BANK 1 RIGHT

X

X

L

X

BANK 2 RIGHT

X

X

X

L

BANK 3 RIGHT

3592 tbl 13