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74LVC623ADB Datasheet(PDF) 2 Page - NXP Semiconductors

Part # 74LVC623ADB
Description  Octal transceiver with dual enable 3-State
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC623ADB Datasheet(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC623A
Octal transceiver with dual enable (3-State)
2
1998 Jul 29
853-2106 19803
FEATURES
Wide supply voltage range of 1.2V to 3.6V
In accordance with JEDEC standard no. 8-1A
Flow-through pin-out architecture
CMOS low power consumption
Inputs accept voltages up to 5.5V
Direct interface with TTL levels
Output drive capability 50W transmission lines @ 85°C
DESCRIPTION
The 74LVC623A is a high performance, low-power, low-voltage
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC623A is an octal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
This octal bus transceiver is designed for asynchronous two-way
communication between data buses.
The control function implementation allows maximum flexibility in
timing. This device allows data transmission from the A bus to the B
bus or from the B bus to the A bus, depending upon the levels at the
enable inputs (OEAB, OEBA). The enable inputs can be used to
disable the device so that the buses are effectively isolated. The
dual enable function configuration gives this transceiver the
capability to store data by simultaneous enabling of OEAB and
OEBA. Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are enabled and all
other data sources to the two sets of the bus lines are at high
impedance OFF-state, both sets of bus lines will remain at their last
states. The 8-bit codes appearing on the two sets of buses will be
identical.
The ‘623A’ is identical to the ‘620A’ but has true (non-inverting)
outputs.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An to Bn; Bn to An
CL = 50pF
VCC = 3.3V
3.3
ns
CI
Input capacitance
5.0
pF
CI/O
Input/output capacitance
10
pF
CPD
Power dissipation capacitance per latch
Notes 1, 2
32
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi )Σ (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic SO
–40
°C to +85°C
74LVC623A D
74LVC623A D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°C to +85°C
74LVC623A DB
74LVC623A DB
SOT339-1
20-Pin Plastic TSSOP Type I
–40
°C to +85°C
74LVC623A PW
7LVC623APW DH
SOT360-1


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