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W65C22S6TPG-14 Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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W65C22S6TPG-14 Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
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10 / 46 page  The Western Design Center, Inc. W65C22S Data Sheet The Western Design Center W65C22S 10 Table 1-3 ORA, IRA Operation for Register 1 ($01) 7 6 5 4 3 2 1 0 ORA,IRA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Pin Data Direction Selection WRITE READ DDRA="1" (Output) (Input latching disabled) MPU writes Output Level (ORA) MPU reads level on PA pin. DDRA="1" (Output) (Input latching enabled) MPU reads IRA bit which is the level of the PA pin at the time of the last CA1 active transition. DDRA="0" (Input) (Input latching disabled) MPU writes into ORA, but no effect on pin level, until DDRA changed. MPU read level on PA pin. DDRA="0 (Input) (Input latching enabled) MPU reads IRA bit which is the level of the PA pin at the time of the last CA1 active transition. Table 1-4 DDRB, DDRA Operation ($02,$03) 7 6 5 4 3 2 1 0 DDRB,DDRA PB7/PA7 PB6/PA6 PB5/PA5 PB4/PA4 PB3/PA3 PB2/PA2 PB1/PA1 PB0/PA0 "0" Associated PB/PA pin is an input (high impedance) "1" Associated PB/PA pin is an output, whose level is determined by ORB/ORA Bit. 1.2. Data Transfer - Handshake Control A powerful feature of the W65C22S is its ability to provide absolute control over data transfers between the microprocessor and peripheral devices. This control is accomplished by way of "handshake" lines. PA lines Peripheral A Control 1,2 (CA1, CA2) handshake data transfers on both Read and Write operations, while PB lines Peripheral B Control 1,2 (CB1, CB2) handshake data on Write operations only. |
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