DS1857E-050 datasheet(4/22 Pages) MAXIM

Part #	DS1857E-050

Description	Dual Temperature-Controlled Resistors with External Temperature Input and Monitors

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Manufacturer	MAXIM [Maxim Integrated Products]

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Dual Temperature-Controlled Resistors with

External Temperature Input and Monitors

4

_____________________________________________________________________

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Fast mode (Note 10)

0

400

SCL Clock Frequency

fSCL

Standard mode (Note 10)

0

100

kHz

Fast mode (Note 10)

1.3

Bus Free Time Between STOP and

START Condition

tBUF

Standard mode (Note 10)

4.7

µs

Fast mode (Notes 10, 11)

0.6

Hold Time (Repeated)

START Condition

tHD:STA

Standard mode (Notes 10, 11)

4.0

µs

Fast mode (Note 10)

1.3

Low Period of SCL Clock

tLOW

Standard mode (Note 10)

4.7

µs

Fast mode (Note 10)

0.6

High Period of SCL Clock

tHIGH

Standard mode (Note 10)

4.0

µs

Fast mode (Notes 10, 12, 13)

0

0.9

Data Hold Time

tHD:DAT

Standard mode (Notes 10, 12, 13)

0

µs

Fast mode (Note 10)

100

Data Setup Time

tSU:DAT

Standard mode (Note 10)

250

ns

Fast mode (Note 10)

0.6

Start Setup Time

tSU:STA

Standard mode (Note 10)

4.7

µs

Fast mode (Note 13)

20 + 0.1CB

300

Rise Time of Both SDA and SCL

Signals

tF

Standard mode (Note 13)

20 + 0.1CB

1000

ns

Fast mode (Note 13)

20 + 0.1CB

300

Fall Time of Both SDA and SCL

Signals

tR

Standard mode (Note 13)

20 + 0.1CB

300

ns

Fast mode

0.6

Setup Time for STOP Condition

tSU:STO

Standard mode

4.0

µs

Capacitive Load for Each Bus Line

CB

(Note 13)

400

pF

EEPROM Write Time

tW

(Note 14)

10

ms

AC ELECTRICAL CHARACTERISTICS

(VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.)

Note 1: All voltages are referenced to ground.

Note 2: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off. The address inputs should be

connected to either VCC or GND depending on the desired address setting.

Note 3: SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels.

Note 4: The maximum voltage the MON inputs will read is approximately 2.5V, even if the voltage on the inputs is greater than 2.5V.

Note 5: This voltage is defining the maximum range of the analog-to-digital converter and not the maximum VCC voltage.

Note 6: Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a

straight line from measured minimum position to measured maximum position.

Note 7: Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change

is the slope of the straight line from measured minimum position to measured maximum position.

Note 8: See the Typical Operating Characteristics.

Note 9: The conversion accuracy does not include any error from the LM50.

Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This

is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns

before the SCL line is released.

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