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P87C554SBBD Datasheet(PDF) 10 Page - NXP Semiconductors |
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P87C554SBBD Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 76 page  Philips Semiconductors Preliminary specification 80C554/83C554/87C554 80C51 8-bit microcontroller – 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP 2000 Nov 10 10 Table 2. External Pin Status During Idle and Power-Down Modes MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PWM0/ PWM1 Idle Internal 1 1 Data Data Data Data Data High Idle External 1 1 Float Data Address Data Data High Power-down Internal 0 0 Data Data Data Data Data High Power-down External 0 0 Float Data Data Data Data High With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down. POWER OFF FLAG The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the 8xC554 rises from 0 to 5 V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3 V for the POF to remain unaffected by the VCC level. Design Consideration • When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. ONCE ™ Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Reduced EMI Mode The ALE-Off bit, AO (AUXR.0) can be set to disable the ALE output. It will automatically become active when required for external memory accesses and resume to the OFF state after completing the external memory access. If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (00X00000). SU00954 IDL BIT SYMBOL FUNCTION PCON.7 SMOD1 Double Baud rate bit. When set to logic 1, the baud rate is doubled when the serial port SIO0 is being used in modes 1, 2, or 3. PCON.6 SMOD0 Selects SM0/FE for SCON.7 bit. PCON.5 POF Power Off Flag PCON.4 WLE Watchdog Load Enable. This flag must be set by software prior to loading timer T3 (watchdog timer). It is cleared when timer T3 is loaded. PCON.3 GF1 General-purpose flag bit. PCON.2 GF0 General-purpose flag bit. PCON.1 PD Power-down bit. Setting this bit activates the power-down mode. It can only be set if input EW is high. PCON.0 IDL Idle mode bit. Setting this bit activates the Idle mode. PD GF0 GF1 WLE POF SMOD0 SMOD1 0 1 2 3 4 5 6 7 (LSB) (MSB) PCON (87H) Figure 3. Power Control Register (PCON) |
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