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P80C528FBBB Datasheet(PDF) 10 Page - NXP Semiconductors

Part # P80C528FBBB
Description  CMOS single-chip 8-bit microcontroller
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P80C528FBBB Datasheet(HTML) 10 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
80C528/83C528
CMOS single-chip 8-bit microcontrollers
1995 Feb 02
10
– setting Read Bit Finished (RBF) when the
SCL clock pulse has finished and Write Bit
Finished (WBF) if there is no arbitration
loss detected (i.e., SDA = 0 while SDO = 1)
– setting a serial clock Low-to-High detected
(CLH) flag
– setting a Bus Busy (BB) flag on a START
condition and clearing this flag on a STOP
condition
– releasing the SCL line and clearing the
CLH, RBF and WBF flags to resume
transfer of the next serial data bit
– generating an automatic clock if the single
bit data register S1BIT is used in master
mode.
The following functions must be done in
software:
– handling the I2C START interrupts
– converting serial to parallel data when
receiving
– converting parallel to serial data when
transmitting
– comparing the received slave address with
its own
– interpreting the acknowledge information
– guarding the I2C status if RBF or WBF = 0.
Additionally, if acting as master:
– generating START and STOP conditions
– handling bus arbitration
– generating serial clock pulses if S1BIT is
not used.
Three SFRs control the bit-level I2C interface:
S1INT, S1BIT and S1SCS.
INTERRUPT SYSTEM
The interrupt structure of the 8XC528 is the
same as that used in the 80C51, but includes
two additional interrupt sources: one for the
third timer/counter, T2, and one for the I2C
interface. The interrupt enable and interrupt
priority registers are IE and IP.
IE: Interrupt Enable Register
This register is located at address A8H. Refer
to Table 3.
IE SFR (A8H)
ET1
ES
ES1
ET2
EA
EX1
ET0
EX0
7
6
5
4
3
2
1
0
IP: Interrupt Priority Register
This register is located at address B8H. Refer
to Table 4.
IP SFR (B8H)
PT1
PS
PS1
PT2
PX1
PT0
PX0
7
6
5
4
3
2
1
0
The interrupt vector locations and the
interrupt priorities are:
Source
Priority within Level
Vector
Address
0003H
IE0
Highest
002BH
TF2+EXF2
0053H
SI (I2C)
000BH
TF0
0013H
IE1
001BH
TF1
0023H
R1+T1
Lowest
Table 3.
Description of IE Bits
MNEMONIC
BIT
FUNCTION
EA
IE.7
General enable/disable control:
0 = NO interrupt is enabled.
1 = ANY individually enabled interrupt will be accepted.
ES1
IE.6
Enable bit-level I2C I/O interrupt
ET2
IE.5
Enable Timer 2 interrupt
ES
IE.4
Enable Serial Port interrupt
ET1
IE.3
Enable Timer 1 interrupt
EX1
IE.2
Enable External interrupt 1
ET0
IE.1
Enable Timer 0 interrupt
EX0
IE.0
Enable External interrupt 0
Table 4.
Description of IP Bits
MNEMONIC
BIT
FUNCTION
IP.7
Reserved.
PS1
IP.6
Bit-level I2C interrupt priority level
PT2
IP.5
Timer 2 interrupt priority level
PS
IP.4
Serial Port interrupt priority level
PT1
IP.3
Timer 1 interrupt priority level
PX1
IP.2
External Interrupt 1 priority level
PT0
IP.1
Timer 0 interrupt priority level
PX0
IP.0
External Interrupt 0 priority level


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