Philips Semiconductors

Product specification

80C851/83C851

CMOS single-chip 8-bit microcontroller

with on-chip EEPROM

1998 Jul 03

10

OSCILLATOR

CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,

respectively, of an inverting amplifier. The

pins can be configured for use as an on-chip

oscillator, as shown in the logic symbol,

page 3.

To drive the device from an external clock

source, XTAL1 should be driven while XTAL2

is left unconnected. There are no

requirements on the duty cycle of the

external clock signal, because the input to

the internal clock circuitry is through a

divide-by-two flip-flop. However, minimum

and maximum high and low times specified in

the data sheet must be observed.

RESET

A reset is accomplished by holding the RST

pin high for at least two machine cycles (24

oscillator periods), while the oscillator is

running. To insure a good power-up reset, the

RST pin must be high long enough to allow

the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At

come up at the same time for a proper

start-up.

Note: Before entering the idle or power-down

modes, the user has to ensure that there is

no EEPROM erase/write cycle in progress

(i.e., the EWP bit has to be reset before

activating the idle or power-down modes;

otherwise EEPROM accesses will be

aborted).

IDLE MODE

In idle mode, the CPU puts itself to sleep

while all of the on-chip peripherals stay

active. The instruction to invoke the idle

mode is the last instruction executed in the

normal operating mode before the idle mode

is activated. The CPU contents, the on-chip

RAM, and all of the special function registers

remain intact during this mode. The idle

mode can be terminated either by any

enabled interrupt (at which time the process

is picked up at the interrupt service routine

and continued), or by a hardware reset which

starts the processor in the same manner as a

power-on reset.

POWER-DOWN MODE

In the power-down mode, the oscillator is

stopped and the instruction to invoke

power-down is the last instruction executed.

Only the contents of the on-chip RAM and

EEPROM are preserved. A hardware reset is

the only way to terminate the power-down

mode. The control bits for the reduced power

modes are in the special function register

PCON. Table 3 shows the state of the I/O

ports during low current operating modes.

INTERRUPT SYSTEM

External events and the real-time-driven

on-chip peripherals require service by the

CPU asynchronous to the execution of any

particular section of code. To tie the

asynchronous activities of these functions to

normal program execution, a multiple-source,

two-priority-level, nested interrupt system is

provided. Interrupt response latency is from

3

S83C851 acknowledges interrupt requests

from 7 sources as follows:

– INT0 and INT1: externally via pins 12 and

13, respectively,

– Timer 0 and timer 1: from the two internal

counters,

– Serial port: from the internal serial I/O port

or EEPROM (1 vector).

Each interrupt vectors to a separate location

in program memory for its service program.

Each source can be individually enabled (the

EEPROM interrupt can only be enabled when

the serial port interrupt is enabled) or

disabled and can be programmed to a high or

low priority level. All enabled sources can

also be globally disabled or enabled. Both

external interrupts can be programmed to be

level-activated and are active low to allow

“wire-ORing” of several interrupt sources to

one input pin.

Note: The serial port and EEPROM interrupt

flags must be cleared by software; all other

flags are cleared by hardware.

Table 3.

External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

1

1

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Power-down

Internal

0

0

Data

Data

Data

Data

Power-down

External

0

0

Float

Data

Data

Data

PARAMETER

RATING

UNIT

Storage temperature range

–65 to +150

–0.5 to +6.5

V

Input or output DC current on any single I/O pin

mA

Power dissipation (based on package heat transfer limitations, not device power consumption)

1.0

W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

noted.