Philips Semiconductors

Preliminary specification

83C748/87C748

80C51 8-bit microcontroller family

2K/64 OTP/ROM, low pin count

1999 Apr 15

8

DIFFERENCES BETWEEN THE 8XC748 AND THE

80C51

Memory Organization

The central processing unit (CPU) manipulates operands in two

address spaces as shown in Figure 3. The part’s internal memory

space consists of 2k bytes of program memory, and 64 bytes of data

RAM overlapped with the 128-byte special function register area.

The differences from the 80C51 are in RAM size (64 bytes vs. 128

bytes), in external RAM access (not available on the 83C748), in

internal ROM size (2k bytes vs. 4k bytes), and in external program

memory expansion (not available on the 83C748). The 128-byte

special function register (SFR) space is accessed as on the 80C51

with some of the registers having been changed to reflect changes

in the 83C748 peripheral functions. The stack may be located

anywhere in internal RAM by loading the 8-bit stack pointer (SP). It

should be noted that stack depth is limited to 64 bytes, the amount

of available RAM. A reset loads the stack pointer with 07 (which is

pre-incremented on a PUSH instruction).

Program Memory

On the 8XC748, program memory is 2048 bytes long and is not

externally expandable, so the 80C51 instructions MOVX, LJMP, and

LCALL are not implemented. The only fixed locations in program

memory are the addresses at which execution is taken up in

response to reset and interrupts, which are as follows:

Program Memory

Event

Address

Reset

000

External INT0

003

Counter/timer 0

00B

External INT1

013

Timer I

01B

Counter/Timer Subsystem

The 8XC748 has one counter/timer called timer/counter 0. Its

operation is similar to mode 2 operation on the 80C51, but is

extended to 16 bits with 16 bits of autoload. The controls for this

counter are centralized in a single register called TCON.

Timer I is available for use as a fixed 10-bit time-base, or as a

watchdog.

Counter Timer – Special Function Register

The counter/timer has only one mode of operation, so the TMOD

SFR is not used. There is also only one counter/timer, so there is no

need for the TL1 and TH1 SFRs found on the 80C51. These have

been replaced on the 8XC748 by RTL and RTH, the counter/timer

reload registers. Table 2 shows the special function registers, their

locations, and reset values.

Interrupt Subsystem – Fixed Priority

The IP register and the 2-level interrupt system of the 80C51 are

eliminated. Simultaneous interrupt conditions are resolved by a

single-level, fixed priority as follows:

Highest priority:

Pin INT0

Counter/timer flag 0

Pin INT1

Lowest priority:

Timer I

Special Function Register – Interrupt Subsystem

Because the interrupt structure is single level on the 83C748, there

is no need for the IP SFR, so it is not used.

Special Function Register –

Serial Communications

The 8XC748 contains many of the special function registers (SFR)

that are found on the 80C51. Due to the different peripheral features

on the 8XC748, there are several additional SFRs. Since the UART

found on 80C51 has been removed, the UART SFRs SCON and

SBUF have also been removed.

I/O Port Latches (P0, P1, P3)

The port latches function the same as those on the 80C51. Since

there is no port 2 on the 83C748, the P2 latch is not used. Port 0 on

the 83C748 has only 3 bits, so only 3 bits of the P0 SFR have a

useful function.

Data Pointer (DPTR)

The data pointer (DPTR) consists of a high byte (DPH) and a low

byte (DPL). In the 80C51 this register allows the access of external

data memory using the MOVX instruction. Since the 83C748 does

not support MOVX or external memory accesses, this register is

generally used as a 16-bit offset pointer of the accumulator in a

MOVC instruction. DPTR may also be manipulated as two

independent 8-bit registers.

Special

Function

Registers

Internal Data

RAM

(FFH) 255

(80H) 128

(3FH) 63

(00H) 0

SU00299

Figure 3. Memory Map