NOVEMBER 1997 - REVISED FEBRUARY 2005

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

Capacitance

TISP4xxxH3LM Overvoltage Protector Series

APPLICATIONS INFORMATION

The protector characteristic off-state capacitance values are given for d.c. bias voltage, VD, values of 0, -1 V, -2 V and -50 V. Where possible,

values are also given for -100 V. Values for other voltages may be calculated by multiplying the VD = 0 capacitance value by the factor given in

Figure 6. Up to 10 MHz, the capacitance is essentially independent of frequency. Above 10 MHz, the effective capacitance is strongly

dependent on connection inductance. In many applications, such as Figure 15 and Figure 17, the typical conductor bias voltages will be about

-2 V and -50 V. Figure 7 shows the differential (line unbalance) capacitance caused by biasing one protector at -2 V and the other at -50 V.

Normal System Voltage Levels

The protector should not clip or limit the voltages that occur in normal system operation. For unusual conditions, such as ringing without the

line connected, some degree of clipping is permissible. Under this condition, about 10 V of clipping is normally possible without activating the

ring trip circuit.

Figure 10 allows the calculation of the protector VDRM value at temperatures below 25 °C. The calculated value should not be less than the

maximum normal system voltages. The TISP4260H3LM, with a VDRM of 200 V, can be used for the protection of ring generators producing

100 V rms of ring on a battery voltage of -58 V (Th2 and Th3 in Figure 17). The peak ring voltage will be 58 + 1.414*100 = 199.4 V. However,

this is the open circuit voltage and the connection of the line and its equipment will reduce the peak voltage. In the extreme case of an

unconnected line, clipping the peak voltage to 190 V should not activate the ring trip. This level of clipping would occur at the temperature

when the VDRM has reduced to 190/200 = 0.95 of its 25 °C value. Figure 10 shows that this condition will occur at an ambient temperature of

-22 °C. In this example, the TISP4260H3LM will allow normal equipment operation provided that the minimum expected ambient

temperature does not fall below -22 °C.

JESD51 Thermal Measurement Method

To standardize thermal measurements, the EIA (Electronic Industries Alliance) has created the JESD51 standard. Part 2 of the standard

(JESD51-2, 1995) describes the test environment. This is a 0.0283 m3 (1 ft 3) cube which contains the test PCB (Printed Circuit Board)

horizontally mounted at the center. Part 3 of the standard (JESD51-3, 1996) defines two test PCBs for surface mount components; one for

packages smaller than 27 mm (1.06 ’’) on a side and the other for packages up to 48 mm (1.89 ’’). The LM package measurements used the

smaller 76.2 mm x 114.3 mm (3.0 ’’ x 4.5 ’’) PCB. The JESD51-3 PCBs are designed to have low effective thermal conductivity (high thermal

resistance) and represent a worse case condition. The PCBs used in the majority of applications will achieve lower values of thermal resistance

and so can dissipate higher power levels than indicated by the JESD51 values.