MAY 1998 - REVISED FEBRUARY 2005

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

TISP8200M & TISP8201M

Figure 9. Voltage Overshoot Referenced to Gate Bias Voltage

TISP8200M 2/10 OVERSHOOT

Time - ns

0

100 200 300 400 500 600 700 800 900 1000

-20

-10

0

10

20

AI8XAMA

(I

V

TISP8201M 2/10 OVERSHOOT

Time - ns

0

100

200

300

400

500

-20

-10

0

10

20

AI8XANA

(I

V

Figure 10. Line Protection with TISP8200M and TISP8201M

C1

100 nF

SLIC

V

BATH

C2

100 nF

V

BATR

0 V

0 V

TISP

8201M

RING

TIP

R1

GR-1089-CORE

R1 = 15

Ω

Ω

Ω

ITU-T K.20 & K.21

R1 = 10 Ω

Ω

Ω

Ω min for coordination

R1

TISP

8200M

AI8XAE

Figure 9 shows typical overshoots on a 100 A 2/10 waveshape. Both devices are under 10 V peak, which meets the needs of the SLICs listed

earlier.

TISP8200M and TISP8201M Voltage Overshoot

Figure 10 shows a typical circuit for single line protection using one TISP8200M and one TISP8201M. The series resistor values limit the test

impulse currents to within the protector ratings.

Line Protection with TISP8200M and TISP8201M