AD9287BCPZRL-100 datasheet(6/52 Pages) AD

Part #	AD9287BCPZRL-100

Description	Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter

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AD9287

Rev. 0 | Page 6 of 52

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9287-100

Parameter1

Temp

Min

Typ

Max

Unit

CLOCK2

Maximum Clock Rate

Full

100

MSPS

Minimum Clock Rate

Full

10

MSPS

Clock Pulse Width High (tEH)

Full

5

ns

Clock Pulse Width Low (tEL)

Full

5

ns

OUTPUT PARAMETERS2

Propagation Delay (tPD)

Full

2.0

2.7

3.5

ns

Rise Time (tR) (20% to 80%)

Full

300

ps

Fall Time (tF) (20% to 80%)

Full

300

ps

FCO Propagation Delay (tFCO)

Full

2.0

2.7

3.5

ns

DCO Propagation Delay (tCPD)3

Full

tFCO +

(tSAMPLE/16)

ns

DCO to Data Delay (tDATA)3

Full

(tSAMPLE/16) − 300

(tSAMPLE/16)

(tSAMPLE/16) + 300

ps

DCO to FCO Delay (tFRAME)3

Full

(tSAMPLE/16) − 300

(tSAMPLE/16)

(tSAMPLE/16) + 300

ps

Data to Data Skew

(tDATA-MAX − tDATA-MIN)

Full

±50

±150

ps

Wake-Up Time (Standby)

25°C

600

ns

Wake-Up Time (Power Down)

25°C

375

μs

Pipeline Latency

Full

10

CLK cycles

APERTURE

Aperture Delay (tA)

25°C

500

ps

Aperture Uncertainty (Jitter)

25°C

<1

ps rms

Out-of-Range Recovery Time

25°C

2

CLK cycles

1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

2 Can be adjusted via the SPI interface.

3 tSAMPLE/16 is based on the number of bits multiplied by 2; delays are based on half duty cycles.

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