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ADG795ACCPZ-REEL Datasheet(PDF) 8 Page - Analog Devices |
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ADG795ACCPZ-REEL Datasheet(HTML) 8 Page - Analog Devices |
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8 / 24 page  ADG795A/ADG795G Rev. 0 | Page 8 of 24 Parameter1 Conditions Min Max Unit Description t11 Standard mode 1000 ns tRCL, rise time of SCL signal Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 40 ns CB = 400 pF max 20 80 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 80 ns CB = 400 pF max 20 160 ns t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 40 ns CB = 400 pF max 20 80 ns tSP Fast mode 0 50 ns Pulse width of suppressed spike High speed mode 0 10 ns 1Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD. 2A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. TIMING DIAGRAM SCL SDA PS S P t8 t6 t5 t3 t10 t9 t4 t6 t1 t7 t2 t11 t12 Figure 2. Timing Diagram for 2-Wire Serial Interface |
Similar Part No. - ADG795ACCPZ-REEL |
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Similar Description - ADG795ACCPZ-REEL |
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