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UCC38503 Datasheet(PDF) 5 Page - Texas Instruments |
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UCC38503 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 31 page ![]() UCC28500, UCC28501, UCC28502, UCC28503 UCC38500, UCC38501, UCC38502, UCC38503 SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001 5 www.ti.com electrical characteristics TA = 0°C to 70°C for the UCC3850X, –40°C to 85°C for the UCC2850X, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 330 pF (unless otherwise noted) PFC gate driver PARAMETER TEST CONDITIONS MIN TYP MAX UNITS GT1 pull up resistance IOUT from −100 mA to –200 mA 5 12 Ω GT1 pull down resistance IOUT = 100 mA 2 10 Ω GT1 output rise time CLOAD = 1 nF, RLOAD = 10 Ω VGT1 from 0.7 V to 9.0 V 25 50 ns GT1 output fall time CLOAD = 1 nF, RLOAD = 10 Ω VGT1 from 9.0 V to 0.7 V 10 50 ns Maximum duty cycle 93% 95% 100% Minimum controlled duty cycle f = 100 kHZ 2% second stage undervoltage lockout (UVLO2) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS PWM turn-on reference (UCCx8500/501) 6.30 6.75 7.30 V Hysteresis (UCCx8500/501) 0.96 1.20 1.44 V PWM turn−on reference (UCCx8502/503) 6.30 6.75 7.30 V Hysteresis (UCCx8502/503) 2.4 3 3.6 V second stage soft-start PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SS2 charge current –7.3 –10 –12.5 µA Input voltage (VERR) IVERR = 2 mA,UVLO = Low 300 mV SS2 discharge current ENBL = High, UVLO = Low, SS2 = 2.5 V 3 10 mA second stage duty cycle clamp PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Maximum duty cycle 44% 50% second stage pulse-by-pulse current sense PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Current sense comparator threshold VERR = 2.5 V measured on ISENSE2 0.94 1.05 1.15 V second stage overcurrent limit PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Peak current comparator threshold 1.15 1.30 1.45 V Input bias current 50 nA second stage gate driver PARAMETER TEST CONDITIONS MIN TYP MAX UNITS GT2 pull up resistance IOUT from −100 mA to –200 mA 5 12 Ω GT2 pull down resistance IOUT = 100 mA 3 10 Ω GT2 output rise time CLOAD = 1 nF,RLOAD = 10 Ω VGT2 from 0.7 V to 9.0 V 25 50 ns GT2 output fall time CLOAD = 1 nF,RLOAD = 10 Ω VGT2 from 9.0 V to 0.7 V 25 50 ns NOTES: 1. Ensured by design. Not production tested. 2. See Figure 6 for reference variation. 3. See Figure 5 for reference variation for VCC < 10.8 V . |
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