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ADP3196 Datasheet(PDF) 8 Page - Analog Devices |
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ADP3196 Datasheet(HTML) 8 Page - Analog Devices |
8 / 20 page ADP3196 Rev. 0 | Page 8 of 20 Pin No. Mnemonic Description 19 OD Output Disable Logic Output. This pin is actively pulled low when the ADP3196 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. 20 IREF Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS, IILIMIT and ITTSENSE. 21 IMON Analog Output. Represents total load current. 22 to 25 SW4 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. 26, 32, 33, 40 NC No Connection. 27 to 30 PWM4 to PMW1 Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120A. Connecting the PWM3 and/or PWM4 outputs to the ADP3196 VCC pin causes that phase to turn off, allowing the ADP3196 to operate as a 2-, 3-, or 4-phase controller. 31 VCC A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5 V. 34 to 39 VID5 to VID0 Voltage Code DAC Inputs. These six pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3750 V and 1.55 V (see Table 4). |
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