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AD995PCBZ Datasheet(PDF) 5 Page - Analog Devices |
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AD995PCBZ Datasheet(HTML) 5 Page - Analog Devices |
5 / 38 page PRELIMINARY TECHNICAL DATA AD9957 Rev. PrF | Page 5 of 38 Parameter Min Typ Max Unit CMOS LOGIC OUTPUTS (1 mA Load) Logic 1 Voltage 2.8 V Logic 0 Voltage 0.4 V XTAL OUTPUT BUFFER SPECS Logic 1 Voltage 1.6 V Logic 0 Voltage TBD V Output Current TBD mA POWER CONSUMPTION DVDD_I/O(3.3V) current consumption (QDUC mode) mA DVDD(1.8V) current consumption (QDUC mode) mA AVDD(3.3V) current consumption (QDUC mode) mA AVDD(1.8V) current consumption (QDUC mode) mA Single Tone Mode 500 mW Continuous Modulation 255x Interpolation TBD 1000 mW Continuous Modulation 4x Interpolation TBD TBD mW Burst Modulation (25%) 255x Interpolation TBD TBD mW Burst Modulation (25%) 4x Interpolation TBD TBD mW Full-Sleep Mode TBD TBD mW Inverse Sinc Filter Power Consumption 150 TBD mW 1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise performance of the device. 2 Wake-up time refers to the recovery from analog power-down modes. 3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the ex- ternal reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the SYSCLK frequency is the same as the external reference clock frequency. Figure 2 Equivalent Input/Output (I/O) Circuits |
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