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HDMP-1637A Datasheet(PDF) 9 Page - Agilent(Hewlett-Packard)

Part # HDMP-1637A
Description  Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs
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Manufacturer  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

HDMP-1637A Datasheet(HTML) 9 Page - Agilent(Hewlett-Packard)

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9
HDMP-1637A (Transmitter Section)
Output Jitter Characteristics (measured with equivalent parts which have TTL REFCLK input)
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Typ.
RJ[1]
Random Jitter at DOUT, the High Speed Electrical Data Port, specified as
ps
8
1 sigma deviation of the 50% crossing point (RMS)
DJ[1]
Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk)
ps
25
Note: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement
method shown in Figure 8.
Figure 8. Transmitter Jitter Measurement Method.
HDMP-1637A (TRx)
Thermal and Power Temperature Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Typ.
Max.
PD,TRx[1,2]
Transceiver Power Dissipation, Outputs connected per
mW
620
900
recommended bias terminations with idle pattern
Θjc[3]
Thermal Resistance, Junction to Case
°C/W
11
Notes:
1. PD is obtained by multiplying VCC by ICC and subtracting the power dissipated outside the chip at the high speed bias resistors.
2. Specified with high speed outputs biased with 150
Ω resistors and receiver TTL outputs driving 10 pF loads.
3. Based on independent package testing by Agilent Technologies.
Θja for these devices is 56.1°C/W for the HDMP-1637A. Θja is
measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature in a given
application, use the following: Tj = TC + (Θjc x PD), where TC is the case temperature measured on the top center of the package
and PD is the power being dissipated.
70841B
PATTERN
GENERATOR*
83480A
OSCILLOSCOPE
HDMP-1637A
70311A
CLOCK SOURCE
+ DATA
- DATA
0000011111
TRIGGER
CH1
CH2
+DOUT
-DOUT
REFCLK LOOPEN
Txi[0..9]
PECL
0011111000
(STATIC K28.7)
1.25 GHz
125 MHz
* PATTERN
GENERATOR
PROVIDES A
DIVIDE BY
10 FUNCTION.
A. BLOCK DIAGRAM OF RJ MEASUREMENT METHOD
70841B
PATTERN
GENERATOR
83480A
OSCILLOSCOPE
HDMP-1637A
70311A
CLOCK SOURCE
+ DATA
- DATA
+K28.5, -K28.5
TRIGGER
CH1
CH2
+DOUT
-DOUTi
REFCLK
LOOPEN
Txi[0..9]
1.25 GHz
125 MHz
ENBYTSYNC
Rx[0..9]
-DIN
+DIN
DIVIDE
BY 2
DIVIDE
BY 10
CIRCUIT
(DUAL
OUTPUT)
VARIABLE
DELAY
PECL
B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD


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