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SN74LVC1G0832DCKT Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVC1G0832DCKT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 13 page SN74LVC1G0832 SINGLE 3INPUT POSITIVE ANDOR GATE SCES606 − SEPTEMBER 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) By tying one input to GND or VCC, the SN74LVC1G0832 offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to VCC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to VCC (Y = A + C). NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OUTPUT A B C OUTPUT Y X X H H H HX H X LL L L X L L X = Valid H or L logic diagram (positive logic) 1 3 4 A B Y 6 C FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE 2-Input AND Gate 1 2-Input OR Gate 2 Y = (A • B) + C 3 logic configurations 1 2 3 6 5 4 A Y B VCC A Y B Figure 1. 2−Input AND Gate |
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