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HT82A821R Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT82A821R Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 41 page  HT82A821R Rev. 1.00 11 July 18, 2006 Power Down Operation - HALT The HALT mode is initialized by the ²HALT² instruction and results in the following: · The system oscillator will be turned off but the WDT oscillator remains running (if the WDT oscillator is se- lected). · The contents of the on-chip RAM and registers remain unchanged. · The WDT and WDT prescaler will be cleared and re- counted again (if the WDT clock is from the WDT os- cillator). · All of the I/O ports remain in their original status. · The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig- nal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow per- forms a ²warm reset². After the TO and PDF flags are examined, the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or exe- cuting the ²CLR WDT² instruction and is set when exe- cuting the ²HALT² instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others remain in their original status. The port A wake-up and interrupt methods can be con- sidered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stim- ulus, the program will resume execution of the next in- struction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the inter- rupt is enabled but the stack is full, the program will re- sume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt re- sponse takes place. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up func- tion of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are four ways in which a reset can occur: · RES reset during normal operation · RES reset during HALT · WDT time-out reset during normal operation · USB reset The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ²warm re - set ² that resets only the program counter and SP, leav- ing the other circuits in their original state. Some regis- ters remain unchanged during other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different ²chip resets². TO PDF RESET Conditions 0 0 RESET reset during power-up u u RESET reset during normal operation 0 1 RESET wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: ²u² stands for ²unchanged² To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the sys- tem resets (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. V D D R E S E T Reset Circuit W a r m R e s e t W D T H A L T C o l d R e s e t R E S E T S y s t e m R e s e t S S T 1 0 - b i t R i p p l e C o u n t e r O S C I Reset Configuration t S S T R E S V D D S S T T i m e - o u t C h i p R e s e t Reset Timing Chart |
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