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WED2DL32512V40BI Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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WED2DL32512V40BI Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
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1 / 9 page  1 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED2DL32512V January 2000 Rev. 0 DESCRIPTION The WEDC SyncBurst - SRAM family employs high-speed, low- power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16 SRAMs into a single BGA package to provide 512K x 32 configura- tion. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE), burst control input (ADSC) and byte write enables (BW0-3). Asynchronous inputs include the output enable (OE), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. Write cycles can be from one to four bytes wide, as controlled by the write control inputs. Burst operation can be initiated with the address status controller (ADSC) input. * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. 512Kx32 Synchronous Pipeline Burst SRAM PRELIMINARY* FEATURES s Fast clock speed: 200, 166, 150 & 133MHz s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns s Single +3.3V power supply (VDD) s Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) s Snooze Mode for reduced-power standby s Single-cycle deselect s Common data inputs and data outputs s Individual Byte Write control and Global Write s Clock-controlled and registered addresses, data I/Os and control signals s Burst control (interleaved or linear burst) s Packaging: • 119-bump BGA package s Low capacitive bus loading FIG. 1 BLOCK DIAGRAM PIN CONFIGURATION (TOP VIEW) 123 4 5 67 A VDDQ SA SA NC SA SA VDDQ B NC SA SA ADSC SA SA NC C NC SA SA VDD SA SA NC D DQc NC VSS NC VSS NC DQb E DQc DQc VSS CE VSS DQb DQb F VDDQ DQc VSS OE VSS DQb VDDQ G DQc DQc BWc NC BWb DQb DQb H DQc DQc VSS NC VSS DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK VSS DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd VSS BWE VSS DQa VDDQ N DQd DQd VSS SA1 VSS DQa DQa P DQd NC VSS SA0 VSS NC DQa R NC SA MODE VDD NC SA NC T NC NC SA SA SA NC ZZ U VDDQ DC DC DC DC NC VDDQ DQb DQa SA CLK ADSC OE BWE CE MODE ZZ BWa BWb 512K x 16 SSRAM DQd DQc 512K x 16 SSRAM BWc BWd NOTE: DC = Do Not Connect |
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