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IDT71P74104S300BQ Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT71P74104S300BQ
Description  18Mb Pipelined QDR II SRAM Burst of 4
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT71P74104S300BQ Datasheet(HTML) 9 Page - Integrated Device Technology

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IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Absolute Maximum Ratings(1) (2)
Capacitance (TA = +25°C, f = 1.0MHz)(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDDQ must not exceed VDD during normal operation.
NOTE:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
Symbol
Parameter
Conditions
Max.
Unit
CIN
Input Capacitance
VDD = 1.8V
VDDQ = 1.5V
5pF
CCLK
Clock Input Capacitance
6
pF
CO
Output Capacitance
7
pF
6111 tbl 06
Symbol
Rating
Value
Unit
VTERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
V
VTERM
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD +0.3
V
VTERM
Voltage on Input terminals with
respect to GND
–0.5 to VDD +0.3
V
VTERM
Voltage on Output and I/O
terminals with respect to GND.
–0.5 to VDDQ +0.3
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Continuous Current into Outputs
+ 20
mA
6111 tbl 05
Recommended DC Operating and
Temperture Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Power Supply
Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
1.9
V
VSS
Ground
0
0
0
V
VREF
Input Reference
Voltage
0.68
VDDQ/2
0.95
V
TA
Ambient
Temperature (1)
025
+70
o
c
6111 tbl 04
NOTES:
1) All byte write (
BWx) and nibble write (NWx) signals are sampled on the
rising edge of K and again on
K. The data that is present on the data bus in the
designated byte/nibble will be latched into the input if the corresponding
BWx or
NWx is held low. The rising edge of K will sample the first and third bytes/
nibbles of the four word burst and the rising edge of
K will sample the second
and fourth bytes/nibbles of the four word burst.
2) The availability of the
BWx or NWx on designated devices is described in
the pin description table.
3) The QDRII Burst of four SRAM has data forwarding. A read request that is
initiated on the cycle following a write request to the same address will produce
the newly written data in response to the read request.
Signal
BW0
BW1
BW2
BW3
NW0
NW1
Write Byte 0
L
XX
XX
X
Write Byte 1
X
L
X
X
X
X
Write Byte 2
X
X
L
X
X
X
Write Byte 3
XXX
L
X
X
Write Nibble 0
X
X
X
X
L
X
Write Nibble 1
XXX
XX
L
6111 tbl 09
Write Descriptions(1,2)
NOTE:
1. During production testing, the case temperarure equals the ambient
temperature.


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