CLC5955

3

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PARAMETERS

CONDITIONS

SYMB

TEMP

RATINGS

UNITS

NOTES

MIN

TYP

MAX

2

max conversion rate (ENCODE)

Full

55

75

MSPS

1

min conversion rate (ENCODE)

+25°C

10

MSPS

pulse width high (ENCODE)

50% threshold

Full

9.1

ns

3

pulse width low (ENCODE)

50% threshold

Full

9.1

ns

3

ENCODE falling edge to DATA not valid

Full

8.3

ns

3

ENCODE falling edge to DATA guaranteed valid

Full

17.8

ns

3

rising ENCODE to rising DAV delay

50% threshold

Full

8.3

12.6

ns

3

DATA setup time before rising DAV

Full

ns

3

DATA hold time after rising DAV

Full

ns

3

pipeline latency

Full

3.0

clk cycle

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are

determined from tested parameters.

Absolute Maximum Ratings

-0.5V to +6V

differential voltage between any two grounds

<100mV

analog input voltage range

digital input voltage range

output short circuit duration (one-pin to ground)

infinite

junction temperature

175°C

storage temperature range

-65°C to 150°C

lead solder duration (+300°C)

10sec

ESD tolerance

human body model

2000V

machine model

200V

Note: Absolute maximum ratings are limiting values, to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional

operability under any of these conditions is not necessarily implied. Exposure to

maximum ratings for extended periods may affect device reliability.

Recommended Operating Conditions

+5V ±5%

analog input voltage range

operating temperature range

-40°C to +85°C

Package Thermal Resistance

Package

48-pin TSSOP

56°C/W

16°C/W

Reliability Information

Transistor count

5000

Ordering Information

Model

Temperature Range

Description

CLC5955MTDX

-40°C to +85°C

48-pin TSSOP (TNR 1000 pc reel)

Notes

1) These parameters guaranteed by test.

2) Typical specifications are based on the mean test values of

deliverable converters from the first three diffusion lots.

3) Values guaranteed based on characterization and simulation.

4) See page 8, Figure 3 for ENCODE Inputs circuit.