SN65LVDS125A

SN65LVDT125A

SLLS595A − OCTOBER 2003 − REVISED FEBRUARY 2004

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6

OUTPUT ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOD

Differential output voltage magnitude

See Figure 2

247

350

454

mV

∆VOD

Change in differential output voltage magnitude between logic

states

VID = ±100 mV

−50

50

mV

VOC(SS) Steady-state common-mode output voltage

1.125

1.375

V

∆VOC(SS)

Change in steady-state common-mode output voltage between

logic states

See Figure 3

−50

50

mV

VOC(PP) Peak-to-peak common-mode output voltage

50

150

mV

ICC

Supply current

RL=100Ω, CL = 1 pF

107

145

mA

IOS

Short-circuit output current

VOY or VOZ = 0 V

−27

27

mA

IOSD

Differential short circuit output current

VOD = 0 V

−12

12

mA

IOZ

High-impedance output current

VO = 0 V or VCC

−1

±1

µA

CO

Differential output capacitance

1.2

pF

SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

700

900

1200

tPHL

Propagation delay time, high-to-low-level output

See Figure 4

700

900

1200

ps

tr

Differential output signal rise time (20%−80%)

See Figure 4

210

280

ps

tf

Differential output signal fall time (20%−80%)

210

280

tsk(p)

Pulse skew (|tPHL − tPLH|)(1)

0

50

ps

tsk(o)

Channel-to-channel output skew(2)

150

ps

tsk(pp) Part-to-part skew(3)

150

ps

tjit(per) Period jitter, rms (1 standard deviation)(4)

750 MHz clock input(5)

(see Figure 6)

0.4

3

ps

tjit(cc) Cycle-to-cycle jitter (peak)(4)

750 MHz clock input(6)

(see Figure 6)

4.7

13

ps

tjit(pp) Peak-to-peak jitter(4)

1.5 Gbps 223−1 PRBS input(7)

(see Figure 6)

65

110

ps

tjit(det) Deterministic jitter, peak-to-peak(4)

1.5 Gbps 27−1 PRBS input(8)

(see Figure 6)

56

90

ps

tPHZ

Propagation delay, high-level-to−high-impedance output

6

tPLZ

Propagation delay, low-level-to-high-impedance output

See Figure 5

6

ns

tPZH

Propagation delay, high-impedance -to-high-level output

See Figure 5

300

ns

tPZL

Propagation delay, high-impedance-to-low-level output

300

(1) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.

(2) tsk(o) is the maximum delay time difference between drivers over temperature, VCC, and process.

(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate

with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(4) Jitter specifications are based on design and characteriztion. Stimulus system jitter of 1.9 ps tjit(per), 16 ps tjit(cc). 17 ps tjit(pp), and 7.2 ps tjit(det)

have been subtracted from the values.

(5) Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%), measured over 1000 samples.

(6) Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%).

(7) Input voltage = VID = 200 mV, 223−1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200k samples.

(8) Input voltage = VID = 200 mV, 27−1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%).